A Continuous-time Sigma-delta Modulator with Clock Jitter Tolerant Self-resetting Return-to-zero Feedback DAC

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.4, AUGUST, 2018 ISSN(Print) ISSN(Online) A Continuous-time Sigma-delta Modulator with Clock Jitter Tolerant Self-resetting Return-to-zero Feedback DAC Donghyeok Jeong 1, Jinho Noh 2, Jisoo Lee 2, and Changsik Yoo 1,* Abstract The tolerance of a continuous-time (CT) sigma-delta modulator (SDM) to the sampling clock jitter can be greatly improved by a self-resetting return-to-zero (SR-RZ) feedback digital-to-analog converter (DAC). The pulse width of the SR-RZ DAC output is adaptively determined so the desired amount of charge to be delivered to the loop filter regardless of the sampling clock jitter. Implemented in a 65-nm CMOS process, a third-order 20-kHz bandwidth (BW) CT-SDM with the proposed SR-RZ DAC has 87.4-dB peak signal-to-noise+distortion ratio (SNDR). The CT-SDM shows no performance degradation even with up to 5-% unit interval (UI) root-mean-square (RMS) clock jitter. Index Terms Sigma-delta modulator (SDM), continuous-time (CT), analog-to-digital converter (ADC), digital-to-analog converter (DAC), loop filter, clock jitter, CMOS Manuscript received Nov. 12, 2017; accepted Mar. 4, Department of Electronic Engineering, Hanyang University, Seoul 04763, Korea (Corresponding author: C. Yoo) 2 System LSI division, Samsung electronics, Kiheung, Korea csyoo@hanyang.ac.kr I. INTRODUCTION Continuous-time (CT) sigma-delta modulator (SDM) is a very attractive architecture in realizing a high resolution analog-to-digital converter (ADC) due to its inherent anti-alias filtering [1-4]. The clock jitter, however, has pronounced effect on the feedback digitalto-analog converter (DAC) of a CT-SDM and may limit the achievable signal-to-noise ratio (SNR) [5]. For reduced sensitivity to the clock jitter, the feedback signal can be designed to decay exponentially by employing a switched-capacitor-resistor (SCR) DAC as proposed in [1]. The SCR DAC requires pre-charging of a capacitor and therefore only a fraction of the sampling clock period is allowed for the feedback charge to be delivered to modulator loop filter, which may limit the maximum clock frequency. In [3], the SCR DAC is modified to the full clock period SCR (FCSCR) DAC with which the full clock period is allowed for the feedback charge to be delivered to modulator loop filter. With the SCR DAC or the FCSCR DAC, the peak level of the feedback current can become very large because the same amount of feedback charge has to be delivered to the loop filter with exponentially decaying current waveform. To reduce the peak current level, the switched-capacitor switchedresistor (SCSR) DAC was proposed [4]. For the SCSR DAC, however, precisely controlled multi-phase switching signals have to be generated by a complicated delay line based circuit. In this paper, a self-resetting (SR) return-to-zero (RZ) DAC is proposed which delivers the desired amount of the feedback charge regardless of the amount of the clock jitter. With the proposed SR-RZ DAC, a 20-kHz bandwidth (BW) third-order CT-SDM has been implemented in a 65-nm CMOS process. Section II describes the architecture and circuit implementation of the CT-SDM with the proposed SR-RZ DAC. The experimental results are given in Section III and finally the paper is concluded in Section IV.

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.4, AUGUST, R F1 R F2 R G R F V INP V INN R 1 R 1 C 1 C 2 C 3 R 2 R V V 3 1P 2P V 3P A 1 A 2 A 3 R 2 V 1N V 2N V 3N R 3 R F3 R F3 V OUTP A 4 V OUTN 4-bit quantizer 4 D OUT C 1 C 2 C 3 DAC1 (SR-RZ) R G R F2 R F1 R F DAC2 (NRZ) D-FF DWA CLK Fig. 1. Third-order CT-SDM with the proposed SR-RZ feedback DAC. II. ARCHITECTURE AND IMPLEMENTATION The third-order CT-SDM shown in Fig. 1 has the input feedforward architecture which is known to be capable of removing the input signal component in the loop filter and thereby reducing the signal swings of the integrator outputs. The local feedback by the resistor RG suppresses the in-band noise by introducing a zero in the noise transfer function (NTF). The loop filter is realized with active-rc integrators because of its better linearity than gm-c integrators. The frequency of the sampling clock is 2.56-MHz and thus the over-sampling ratio (OSR) is 64 for the signal BW of 20-kHz. The output of the loop filter is sampled and digitized by a four-bit quantizer whose output is fed back by the DAC1 and the DAC2. The DAC1 employs the proposed jitter-tolerant SR-RZ architecture to ensure the insensitivity to the clock jitter. In order to shape the noise due to the mismatch of the multi-bit DAC1, the output of the quantizer is randomized by the dynamic weight averaging (DWA) block [3]. The DAC2 removes the effect of the excess loop delay (ELD) [2] and is a conventional non-return-to-zero (NRZ) DAC because its output is shaped by the loop filter and therefore insensitive to the clock jitter. The non-linearity of the DAC2 is not a concern because it is placed inside the loop and thus the noise power due to its non-linearity is shaped by the loop filter. CLK VRZEN VREF VCAP RST (a) (b) Fig. 2. (a) Jitter-tolerant SR-RZ feedback DAC, (b) its operating timing. 1. Self-resetting Return-to-zero (SR-RZ) Feedback DAC While a RZ feedback DAC can avoid the performance degradation due to the inter-symbol interference (ISI), it is more sensitive to the clock jitter than a non-return-tozero (NRZ) feedback DAC because both the rising and

3 470 DONGHYEOK JEONG et al : A CONTINUOUS-TIME SIGMA-DELTA MODULATOR WITH CLOCK JITTER TOLERANT Fig. 3. Operational amplifier with feed-forward frequency compensation. falling edges of the clock affect the amount of the feedback charge [7]. With the proposed SR-RZ feedback DAC shown in Fig. 2(a), the immunity to the ISI and excellent tolerance to the clock jitter can be achieved simultaneously. At the rising edge of the clock CLK, the RZ feedback signal is turned on by setting the DAC enabling signal VRZEN to be HIGH as shown in Fig. 2(b). The capacitor C1 begins to be charged by the current source ISRC and when the voltage VCAP across C1 becomes larger than VREF, the DAC enabling signal VRZEN is reset to LOW. The pulse width of VRZEN is then equal to C1VREF/ISRC and the DAC switches are turned on only when VRZEN is HIGH. Therefore, the delivered charge by the feedback DAC to the loop filter is independent of the clock jitter, meaning excellent jitter tolerance. The pulse width, of course, can change by the thermal noise of the current source ISRC and the voltage reference VREF. The current source ISRC is a simple one built with a pmos transistor and the voltage reference VREF is low-pass filtered before being applied to the RZEN generator, the effect of their thermal noise can be controlled to be negligible, which has been verified by the measurement results shown in the next section. 2. Operational Amplifier The operational amplifier (op-amp) of the firstintegrator is designed to have 10-MHz unity-gain BW to (a) (b) Fig. 4. (a) Offset cancelled comparator used for the multi-bit quantization, (b) its clock timing. prevent the leakage of the quantization noise to the output [8]. The unity-gain BW of the op-amps of the second- and third-integrators is designed to be 5-MHz to save power. All the op-amps have the same architecture shown in Fig. 3 which employs the feed-forward frequency compensation [3]. The differential input VINP and VINN are directly applied to the pmos differential pair consisting of the transistors M10 and M11 of the second stage to provide the feed-forward path and thereby create a left-half-plane (LHP) zero which widens the bandwidth without consuming additional power.

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.4, AUGUST, Fig. 5. Chip microphotograph and its layout. Fig. 7. SNDR and SNR versus the input signal amplitude. Fig. 6. Measured output spectrum for 1-kHz input signal. 3. Multi-bit quantizer The loop filter output is quantized by a 4-bit differential flash ADC for which the comparator shown in Fig. 4(a) is used. The comparator has the offset cancelled pre-amplifier followed by the strong-arm latch-type clocked comparator and operates with the clock timing shown in Fig. 4(b). In addition to the offset cancellation, the pre-amplifier reduces the kick-back noise. Although the pre-amplifier is fully differential, it does not need any active common-mode feedback HIGH). When CLKDB becomes HIGH, the difference between the differential inputs and reference levels is amplified by the pre-amplifier and the pre-amplifier output is latched at the rising edge of CLK. The differential reference levels for the quantization are generated by a simple resistive voltage divider. Fig. 8. SNDR of the CT-SDM with the proposed SR-RZ DAC and the conventional RZ DAC versus the sampling clock jitter. Table 1. Comparison of clock jitter tolerance of feedback DAC NRZ DAC [9] SCR DAC [1] SCSR DAC [4] FSCR DAC [3] SR-RZ DAC *proposed Tolerable clock jitter 0.05-% UI RMS 2-% UI RMS 2-% UI RMS 1-% UI RMS 5-% UI RMS III. EXPERIMENTAL RESULTS The third-order 20-kHz BW CT-SDM with the proposed jitter-tolerant SR-RZ DAC has been implemented in a 65-nm CMOS process. The active silicon area of the CT-SDM is 0.6-mm2. The chip microphotograph and its layout are shown in Fig. 5. While consuming 0.45-mW from a 1.2-V supply, the peak signal-to-noise+distortion ratio (SNDR) of the CT-

5 472 DONGHYEOK JEONG et al : A CONTINUOUS-TIME SIGMA-DELTA MODULATOR WITH CLOCK JITTER TOLERANT Table 2. Performance comparison This work [10] [11] [12] [13] [14] [15] [16] [17] [18] Process [nm] Supply [V] Bandwidth [khz] SNDR [db] DR [db] Power [mw] FoM SDM is 87.4-dB as shown in Fig. 6. As a function of the input signal amplitude, the signal-to-noise ratio (SNR) and SNDR are measured as shown in Fig. 7 and the dynamic range (DR) is 89.9-dB. The tolerance of the SR-RZ DAC to the clock jitter can be evaluated by measuring the SNDR of the CT- SDM versus the root-mean-square (RMS) clock jitter as shown in Fig. 8. For fair comparison, the third-order CT- SDM has been designed to choose either the conventional RZ DAC or the proposed SR-RZ DAC as a feedback DAC. As can be seen in the figure, the SNDR does not show any remarkable degradation even with 5- % unit-interval (UI) RMS clock jitter with the proposed SR-RZ DAC while that of the CT-SDM with the conventional RZ DAC decreases by more than 40-dB. The clock jitter tolerance of the proposed SR-RZ DAC is compared with other feedback DACs in Table 1. The tolerable clock jitter is defined as the RMS clock jitter with which the SNDR decreases by 3-dB from its peak value. As can be seen in the table, the proposed SR-RZ DAC shows the best tolerance to the clock jitter. The performance of the CT-SDM of this work is compared with other CT-SDMs in Table 2. For fair comparison, the figure-of-merit (FoM) defined in (1) is used. Although the design of the CT-SDM of this work is focused to improve the immunity to the sampling clock jitter, it shows comparable FoM with the others. IV. CONCLUSIONS Excellent tolerance of a CT-SDM to the ISI and clock jitter can be simultaneously achieved with the proposed SR-RZ DAC. The SR-RZ DAC determines the pulse width of the feedback DAC output so the desired amount of charge to be delivered regardless of the clock jitter. A third-order 20-kHz BW CT-SDM implemented in a 65- nm CMOS process shows no degradation in its SNDR even with up to 5-% UI RMS clock jitter. The proposed SR-RZ DAC can be applied to any type of CT-SDM to get excellent tolerance to sampling clock jitter. ACKNOWLEDGMENTS This work was supported by the R&D program ( ) of MOTIE/KEIT of Korea, the Institute for Information & communications Technology Promotion (IITP) grant (No. R ), and the National Research Foundation of Korea (NRF) grant (NRF- 2016R1D1A1B ) funded by the Korea government (MSIP). The CAD tools and chip fabrication service were provided by the IC Design Education Center (IDEC), Korea. REFERENCES [1] M. Ortmanns, F. Gerfers, and Y. Manoli, A continuous-time ΣΔ modulator with reduced sensitivity to clock jitter through SCR feedback, Circuits and Systems-I, IEEE Transactions on, Vol. 52, No. 5, pp , May., [2] S. Yan and E. Sanchez-Sinencio, A Continuous- Time ΣΔ Modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth, Solid-State Circuits, IEEE Journal of, Vol. 39, No. 1, pp , Jan., [3] J. G. Jo, J. Noh, and C. Yoo, A 20-MHz bandwidth continuous-time sigma-delta modulator with jitter immunity improved full clock period SCR (FSCR) DAC and high-speed DWA, Solid- State Circuits, IEEE Journal of, Vol. 46, No. 11, pp , Nov., [4] M. Anderson and L. Sundstrom, Design and

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.4, AUGUST, measurement of a CT ΔΣ ADC with switchedcapacitor switched-resistor feedback, Solid-State Circuits, IEEE Journal of, Vol. 44, No. 2, pp , Feb., [5] K. Reddy and S. Pavan, Fundamental limitations of continuous-time delta-sigma modulator due to clock jitter., Circuits and Systems-I, IEEE Transactions on, Vol. 54, No. 10, pp , Oct., [6] B. Razavi, The StrongARM latch [a circuit for all seasons], Solid-State Circuits, IEEE Magazine of, Vol. 7, No. 2, pp , Jun., [7] S. Pavan, R. Schreier, G. C. Temes, Nonidealities in continuous-time delta-sigma modulators, in Understanding delta-sigma data converters, 2 nd ed., IEEE Press, 2017, pp [8] M. Ortmanns, F. Gerfers, and Y. Manoli, Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulator, Circuits and Systems-I, IEEE Transactions on, Vol. 51, No. 6, pp , Jun., [9] F. Gerfer, M. Ortmanns, and Y. Manoli, A 1.5-V, 12-bit power efficient continuous-time third-order modulator, Solid-State Circuits, IEEE Journal of, Vol. 38, No. 8, pp , Aug., [10] S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, A power optimized continuous-time ΔΣ ADC for audio applications, Solid-State Circuits, IEEE Journal of, Vol. 43, No. 2, pp , Feb., [11] S. Pavan and P. Sankar, Power reduction in continuous-time delta-sigma modulators using the assisted opamp technique, Solid-State Circuits, IEEE Journal of, Vol. 45, No. 7, pp , Jun., [12] A. Sukumaran and S. Pavan, Low power design techniques for single-bit audio continuous-time delta sigma ADCs using FIR feedback, Solid-State Circuits, IEEE Journal of, Vol. 49, No. 11, pp , Nov., [13] S. Billa, A. Sukumaran, and S. Pavan, A 280 μw 24 khz-bw 98.5 db-sndr chopped single-bit CT ΔΣM achieving < 10 Hz 1/f noise corner without chopping artifacts, Solid-State Circuits, IEEE Conference on, pp , [14] C. D. Berti, P. Malcovati, L. Crespi, and A. Baschirotto, A 106 db A-weighted DR low-power continuous-time ΣΔ modulator for MEMS microphones, Solid-State Circuits, IEEE Journal of, Vol. 51, No. 7, pp , Apr., [15] L. Liu, D. Li, Y. Ye, L. Chen, and Z. Wang, A 95 db SNDR audio delta-sigma modulator in 65 nm CMOS, Custom Integrated Circuits, IEEE Conference on, pp. 1-4, [16] L. Dorrer, F. Kuttner, and A. Santner, A continuous time ADC for voice coding with 92 db DR in 45 nm CMOS, Solid-State Circuits, IEEE Conference on, pp , [17] J. Zhang, Y. Lian, L. Yao, and B. Shi, A 0.6-V 82- db 28.6-μW continuous-time audio delta-sigma modulator, Solid-State Circuits, IEEE Journal of, Vol. 46, No. 10, pp , Oct., [18] K. P. Pun, S. Chatterjee, and P. R. Kinget, A 0.5- V 74-dB SNDR 25-kHz continuous-time deltasigma modulator with a return-to-open DAC, Solid-State Circuits, IEEE Journal of, Vol. 42, No. 3, pp , Apr., circuits design. Donghyeok Jeong received the B.S. degree in electronic engineering from Hanyang University, Seoul, Korea, in 2014 and is currently working toward the Ph.D. degree at the same university. His research interests include data converter integrated Jinho Noh received the B.S. degree in electronic engineering from Dankook University, Seoul, Korea, in 2014, the Ph. D. degree in electronic engineering from Hanyang University, Seoul, Korea, in Since 2016, he has been a Senior Engineer of the system LSI division of Samsung Electronics, Kiheung, Korea. His current research interests include power management and data conversion integrated circuits design.

7 474 DONGHYEOK JEONG et al : A CONTINUOUS-TIME SIGMA-DELTA MODULATOR WITH CLOCK JITTER TOLERANT Jisoo Lee received the B.S. and M. S. degree in electronic engineering from Hanyang University, Seoul, Korea, in 2012 and 2014, respectively. Since 2014, he has been working in the system LSI division of Samsung Electronics, Kiheung, Korea. His current research interests include data conversion integrated circuits design. Changsik Yoo received the B.S. (Honors), M.S., and Ph.D. degrees from Seoul National University, Seoul, Korea, in 1992, 1994, and 1998, respectively, all in electronic engineering. From 1998 to 1999, he was with the Integrated Systems Laboratory (IIS), Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, as a Research Staff. From 1998 to 2002, he was with Samsung Electronics, Hwasung, Korea, as a Senior Engineer. Since 2002, he has been a Professor of Hanyang University, Seoul, Korea. His main research interest is the mixed-mode CMOS integrated circuit design.