THE DEMAND for sensors has enormously expanded due

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1 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 61, NO. 2, FEBRUARY A Bufferless Interface for Single-Ended ECM Sensors Youngkil Choi, Student Member, IEEE, Hyungdong Roh, Student Member, IEEE, and Jeongjin Roh, Senior Member, IEEE Abstract This paper presents a bufferless interface that can be directly connected to a single-ended capacitive sensor such as an electret condenser microphone. A high-input impedance interface is developed using only a continuous-time loop filter, whereas conventional interface circuits are composed of a buffer, a preamplifier, an antialiasing filter, and a high-order switchedcapacitor loop filter. Equipped with an active gm-c integrator, this interface chip is designed to implement all the required functions, i.e., high-input impedance buffering, preamplification, antialiasing filtering, and analog-to-digital conversion. The inherent antialiasing filtering function also provides a significant advantage in terms of silicon areas and power consumption. The complete interface channel achieves a 75-dB dynamic range and a 60.3-dB signal-to-noise-plus-distortion ratio over a 25-kHz signal band, which satisfies the requirements for electret microphones. The power consumption of the interface channel is 600 μw, and the chip dissipates a total of 860 μw from the 3.3-V supply. Index Terms Capacitive sensor, continuous-time (CT) loop filter, delta sigma technology, electret microphone, oversampling, preamplifier. I. INTRODUCTION THE DEMAND for sensors has enormously expanded due to the wide use of consumer electronic products with sensor applications. For this reason, the design of interface circuits has become more important than before [1] [4]. Due to the pressure of higher prices, a higher level of integration and mixture of functions is required for interface circuits. To satisfy these requirements, an efficient interface architecture is needed for interface circuits to monitor various sensors in addition to an electret condenser microphone (ECM). The ECM, which is a kind of capacitive sensor, is an important component in commercial products. Fig. 1(a) shows the ECM package compared with a ring. Fig. 1(b) shows the cross section of the inside of the package. There are four major parts, i.e., 1) a very light diaphragm; 2) back plate; 3) electret material; and 4) interface circuit [5], [6]. Previous circuits were based on analog signal processing using a discrete junction gate field-effect transistor (JFET), Manuscript received February 17, 2011; revised June 13, 2011; accepted June 18, Date of publication August 4, 2011; date of current version January 5, This work was supported in part by the Ministry of Knowledge Economy, Korea, through the University Information Technology Research Center support program supervised by the National IT Industry Promotion Agency under Grant NIPA-2011-C The Associate Editor coordinating the review process for this paper was Dr. Dario Petri. The authors are with the Department of Electrical Engineering, Hanyang University, Ansan , Korea ( jroh@hanyang.ac.kr). Digital Object Identifier /TIM Fig. 1. High-performance compact ECM [6]. (a) High-performance ECM. (b) Cross section of the high-performance ECM. as shown in Fig. 2(a), and their ECM cartridges contained acoustic sensors that sensed voice signals and discrete JFET elements [7]. A JFET, which is used as a signal transmission device, is composed of high-input impedance gates to facilitate signal transmission from capacitive sources [8]. Single-ended outputs from the JFET amplifier pass through the external direct-current (dc) blocking capacitor C B and are delivered to the preamplifier within the CODEC block. The preamplifier is composed of R 1, R 2, C LPF, and A 1. C LPF helps to implement a low-pass filter that removes high-frequency noise. However, the JFET used in the conventional structure has several performance problems. First, the maximum inherent nonlinearity is close to 1% total harmonic distortion, and its power supply rejection ratio is also low, which significantly affects the performance. In addition, the analog signal, processed in the course of a single-ended connection between the output from the JFET and the input of the CODEC block, is easily corrupted by /$ IEEE

2 514 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 61, NO. 2, FEBRUARY 2012 Fig. 2. (a) Conventional ECM+CODEC configuration. (b) Improved digital ECM configuration. (c) Proposed ECM interface channel. Fig. 3. CT integrators [13]. (a) Active gm-c integrator. (b) Active-RC integrator. (c) gm-c integrator. external noise, which limits signal quality. Attempts to improve signal quality include changing the JFET-based interface into a complementary metal oxide semiconductor (CMOS) preamplifier or a single transconductance gm block, as shown in Fig. 2(b) [7], [9] [11]. The interface of the ECM cartridge in Fig. 1(b) has only digital input/output signals, i.e., clock input and data out. These signals, which are different from the output of a conventional JFET ECM cartridge, are very robust against external noise. Differences between Fig. 2(a) and (b) are the existence or nonexistence of the JFET and fewer external discrete elements. However, the preamplifier, which is composed of many elements, remains to remove highfrequency noises at the cost of consuming additional space and power. Fig. 2(c) shows that we have combined all functions essential for high-performance electret microphones into a single continuous-time (CT) loop architecture in order to reduce the silicon area and power consumption. In this CT delta sigma (ΔΣ) interface channel, an active gm-c integrator replaces the JFET-based high-input impedance interface and its signal amplification functions. Due to the CT ΔΣ loop filter s inherent antialiasing characteristics [12], no additional preamplifier is required. Moreover, since this CT ΔΣ modulator consumes less power than the discrete-time (DT) modulators in previous interface circuits, it would be appropriate for low-power mobile ECM devices. II. SYSTEM DESIGN Different circuit techniques have been used to implement the integrators in CT ΔΣ loop filters. Fig. 3 shows the integrators for CT loop filter implementation [13]. As listed in Table I,

3 CHOI et al.: BUFFERLESS INTERFACE FOR SINGLE-ENDED ECM SENSORS 515 TABLE I COMPARISON OF THE INTEGRATORS FOR THE PROPOSED ARCHITECTURE Fig. 4. Block diagram of the proposed ECM interface channel. each type of integrator has advantages and disadvantages. The gm-c integrators [14] are widely used in video, intermediate frequency, or very high frequency applications and have the advantages of high-speed operation and simple structure. Active-RC integrators have the highest linearity due to the feedback structure and high linearity of passive resistors. However, it is necessary to consider other key points for electret microphones. First, in order to achieve a direct connection with microphones, the input impedance of the first integrator must be high; to obtain a wide dynamic range (DR), linearity should be also high. Given that microphones are portable devices, low-power designs are also necessary. It is obvious that to implement a CT ΔΣ interface that meets these requirements, the mixture of an active gm-c integrator and an active-rc integrator is the best combination. Fig. 4 shows the proposed ECM interface sensor. The sensor is based on a single-loop distributed feedforward topology, which is useful in optimizing power consumption [15], [16]. The advantage of the distributed feedforward architecture is that the operational amplifier (opamp) in the loop filter can be designed more efficiently since the loop filter does not process an input signal. The input feedforward path that runs from the input of the interface channel to the front of the quantizer is removed since input impedance must be high to directly connect to the electret microphone. As shown in Fig. 2(a) and (b), a preamplifier block is essential to amplify the weak signals generated by the microphone before the analog-to-digital converter (ADC) block. In the developed interface chip, the in-band signal transfer function (STF) gain is set to four times in order to amplify the maximum peak-to-peak input signal of 300 mv PP to the full-scale input level of the ADC; this setting can be identified by b 1 in Fig. 4. While conventional structures have separate analog front-end Fig. 5. TABLE II LOOP FILTER S COEFFICIENT VALUES Simulated peak SNDR and SNR versus V DC variation. blocks for this operation, the proposed architecture implements this function by controlling the input gm value of the CT ΔΣ interface, resulting in a reduced number of analog components. References [17] and [18] cover the mathematical analysis of the CT ΔΣ modulator, including a half-cycle delay (z 1/2 ).The

4 516 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 61, NO. 2, FEBRUARY 2012 Fig. 6. Schematic of the proposed interface channel. STF and noise transfer function (NTF) of the proposed interface circuit are derived as STF = L 0 (s) NTF 1 NTF = 1 (L 1 (s) z 1 ) L 0 (s) = N A4s 4 + N A3 s 3 + N A2 s 2 s 6 + D A4 s 4 L 1 (s) = N B5s 5 + N B4 s 4 + N B3 s 3 + N B2 s 2 s 6 + D B4 s 4 (1) where N A4 = a 1 b 1 N A3 = a 2 b 1 c 2 N A2 = b 1 (a 1 c 3 g 1 + c 2 c 3 c 4 ) D A4 = c 3 g 1 N B5 = (d 1 + d 2 ) N B4 = a 1 c 1 N B3 = a 2 c 1 c 2 c 3 g 1 (d 1 + d 2 ) N B2 = c 1 c 2 c 3 c 4 + a 1 c 1 c 3 g 1 D B4 = c 3 g 1. The loop coefficients in Fig. 4 are listed in Table II. If the resistors and the capacitors in the CT loop filter suffer from large process variations, their coefficient values can change. To avoid performance degradation due to these variations, an additional tuning circuit should be used in CT circuits [19], [20]. In the case of 3 5 pf microphone capacitive sensors, the bias resistance for setting input dc voltage should be several gigaohms at the very least. Fig. 4 shows that the best method for implementing this large resistance value in the chip is to use a pair of antiparallel diodes. The V DC for biasing antiparallel diodes and a common-mode voltage V CM for the CT interface are obtained from the built-in bandgap reference. The voltages Fig. 7. Schematic of the gm-cell. from the bandgap reference may have a slight variation when supply voltage or temperature changes. Fig. 5 shows the signalto-noise-plus-distortion ratio (SNDR) and signal-to-noise ratio (SNR) according to the bias voltage variations. When the bias voltage is varied up to 1.7 V, harmonic distortions are observed due to the small input common-mode range of the gm-cell, which is shown as an input stage in Fig. 6. The cascoded current source (P1 P4) of the gm-cell in Fig. 7 should be modified to a simple current source to widen the input common-mode range. A. ECM Interface Using Delta Sigma Modulator Conventional ΔΣ modulators for audio signal processing have been implemented using switched-capacitor (SC) circuits that operate in DT. These SC ΔΣ modulators have the advantage of being robust since the coefficients of the loop filters are determined by the ratio of the capacitors. In ECM applications, however, the input impedance must be very high so that the

5 CHOI et al.: BUFFERLESS INTERFACE FOR SINGLE-ENDED ECM SENSORS 517 Fig. 8. Schematic of opamp used in the interface channel. SC circuit cannot be used without a buffer in front of it, which we are trying to avoid. Since we are developing a new ECM interface architecture that is as simple as possible, we excluded the SC circuits from our design. In addition, in SC ΔΣ modulators, the unity-gain frequency F U of the opamp should be at least five times the sampling frequency F S, which results in high power consumption. In comparison, opamps in CT ΔΣ modulators have relatively less severe settling problems; therefore, in theory, their F U can be as low as the F S. Therefore, CT ΔΣ modulators are suitable for systems in which low power consumption is of utmost importance, such as portable devices. Fig. 4 shows that in the case of the CT ΔΣ interface, the input signal will pass through the loop filter characterized as a low-pass filter and will then be sampled at the front of the quantizer. This signal processing provides an inherent antialiasing filter function. Therefore, CT implementation eliminates the need for an extra antialiasing filter in the system, which helps to fulfill the low-power and small-area requirement. Fig. 6 presents the proposed interface channel, including the fourth-order CT ΔΣ modulator. The interface channel has a 1-bit quantizer operating at 3.2 MHz with an oversampling ratio (OSR) of 64. The NTF is designed with the peak value of 1.5 [21], [22], and extensive behavioral simulation is performed to ensure stability under worst case condition. As mentioned earlier, the first integrator uses an active gm-c scheme. For the other integrators, active-rc integrators with excellent linearity are used to construct loop filters. In order to implement an NTF including zero, a resistor R FB is connected between the input of the second integrator and the output of the third integrator. A D flip-flop (D_FF), discussed later, is used to implement the half-cycle feedback delays shown in Fig. 4. The coefficients d 1 and d 2 are implemented using the delayed signals generated by the D_FF and feedback resistors (R DAC2 and R DAC3 ). In order to maximize performance, the overall circuits in the interface channel are implemented by a fully differential architecture. The simulated peak SNDR achieved from the HSPICE tool is 65 db. The test input signal is a kHz sine wave with a 12 dbfs amplitude. The total number of points collected for Fig. 9. RZ DAC. the spectrum analysis is The simulated DR is 80 db in the 25-kHz signal band, and the simulated power consumption of the interface channel is μw. B. Active gm-c Integrator Circuit In general, high-input impedance in common ΔΣ applications is not mandatory. However, as shown in Fig. 6, for the direct connection to the microphone, the first integrator in the interface channel is composed of an active gm-c circuit. Table I shows that active gm-c integrators have high-input impedance and higher linearity than gm-c integrators. In the case of gm-c integrators, the parasitic capacitance values of output nodes can cause linearity problems since these capacitance values affect the integration coefficient. The extra opamp, which is used in the first integrator, reduces the effects of these parasitic capacitance values. The advantage of using this opamp is that the effect of parasitic capacitance values is reduced by the gain of the opamp. Fig. 7 shows the schematic of the gm-cell. The PMOS input pair uses the source degeneration resistor R S ; thus, it is possible to achieve a stable gm value and increased linearity. In addition, signals can easily be amplified by adjusting the size of R S. As mentioned earlier, the maximum signal level generated by an electret microphone is about

6 518 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 61, NO. 2, FEBRUARY 2012 Fig. 10. Test board. Fig. 12. Measured output PSD plot (65536-point FFT) of the electret microphone channel. Fig. 11. Chip photograph. 300 mv PP ; therefore, the signal swing can be considered within the linear range designed by the active gm-c integrator. Fig. 8 shows the schematic of the opamp used in the ΔΣ interface. It is a two-stage class-ab amplifier, where the first stage uses a PMOS input pair, and the second stage uses a class-ab pair. The opamp is Miller compensated using R C1 and C C1, as shown in Fig. 8. The value of C C1 is 500 ff. It can be demonstrated that a two-stage design is more effective in reducing the in-band noise arising from opamp nonlinearity when compared with a single-stage opamp [23]. The open-loop dc gain of the opamp is 73 db with an F U of 17 MHz and a phase margin of 62. A single-ended microphone signal is applied to the INP terminal, as shown in Fig. 6, and is connected to the gate of the PMOS transistor in the gm-cell. The applied signal allows currents to flow through R S by the PMOS input transistors. The current is integrated by the integrating capacitor C 1 in the Fig. 13. Measured DR of the electret microphone channel. first integrator. Processed this way, the signal is converted into differential signals in the first integrator. C. Feedback Digital-to-Analog Converter Design Several digital-to-analog converter (DAC) design issues are critical to the performance of the CT ΔΣ circuits such as feedback pulse distortion, jitter sensitivity, and excess loop delay. A return-to-zero (RZ) scheme [24] is used in the feedback DAC of this ΔΣ interface for low pulse distortion. In the case of a nonreturn-to-zero (NRZ) signaling scheme, even a differential circuit implementation cannot remove the pulse distortion, which degrades the linearity of the whole system. In contrast, by using RZ signaling, the DAC output resets to a constant dc level before the next input comes in, which removes the datadependent transient and improves the linearity of the system. The RZ signal is realized by switching the feedback DAC outputs to a common-mode potential V CM for a short interval

7 CHOI et al.: BUFFERLESS INTERFACE FOR SINGLE-ENDED ECM SENSORS 519 TABLE III CHIP PERFORMANCE SUMMARY AND COMPARISON during the code transitions. The jitter sensitivity depends only on the φ RZ signal shown in Fig. 9. Jitter sensitivity is increased when compared to the NRZ signaling scheme, since the falling edges of the φ RZ signal are not determined by the φ 1 clock transition. Another problem with the CT ΔΣ interface is the nonzero excess loop delay. The excess loop delay, which comprises the delay between the quantizer clock edge and the valid DAC output, causes performance degradation of the entire system. If this delay becomes too long, instability may occur. In order to solve this problem, our design employs a structure [17] to add a half-cycle delay (z 1/2 ) by D_FF, as shown in Fig. 4. By using this structure, not only can interfaces that are relatively less sensitive to delay time be designed but also the requirements for the quantizer can be relaxed. Thus, low-power designs can be achieved. III. MEASUREMENT RESULTS Fig. 10 shows the test setup used to measure the performance of the ECM interface circuit described in this paper. The input to the device under test is generated using an Audio Precision SYS-2712 signal generator. The supply voltages are directly provided by Agilent E3620 with a low-noise property. The interface output bit stream is acquired by the high-quality Agilent logic analyzer 16902A. A 3.2-MHz system clock is supported by the Agilent pulse generator 81130A. In order to reduce the possibility of digital noise interference, separate analog and digital planes, as well as decoupling capacitors, are used in the board [25]. This chip is implemented using a 0.13-μm 1-poly 4-metal (1P4M) CMOS process with a 3.3-V-thick gate oxide option. Fig. 11 shows a photograph of the chip with a silicon area of 0.81 mm 2.TheCTΔΣ interface itself occupies just mm 2 and consumes only 600 μw. The experimental output power spectrum density (PSD) plot [65536-point fast Fourier transform (FFT)] with 16.5 dbfs kHz input signal is shown in Fig. 12. The input frequency used to measure the interface is khz to reduce the effects of spectral leakage on the SNR [26]. Finally, Fig. 13 shows the measured SNR and SNDR versus input levels. The SNDR is degraded as the input level approaches the full scale due to the nonlinearity of the input gm-cell. The fabricated chip achieves a 75-dB DR over a 25-kHz signal bandwidth with an OSR of 64 while dissipating 860 μw from a 3.3-V power supply. The measured performance successfully satisfies the requirements of the ECM applications. Table III summarizes these experimental results, and it lists a performance comparison between the different architectures reported in the literature and in this paper. To evaluate the performance of the interface in the context of some state-of-the-art interfaces, a figure-of-merit (FOM) [13] is shown as follows: P FOM = 2 BW 2. (2) (SNDR p 1.76)/6.02 where P, BW, and SNDR p denote the power consumption, signal bandwidth, and peak SNDR. The smaller the FOM value is, the better the overall performance is. The bufferless interface of this paper achieves the FOM, which is excellent compared with other designs. IV. CONCLUSION This paper has proposed a bufferless ECM interface channel that can be directly connected to electret microphones. Using the characteristics of the CT loop filter extensively, most of the key functions for the ECM interface are incorporated into the CT ΔΣ loop itself. Because the interface architecture is simplified and combined into the modulator, the power consumption and silicon area can be reduced and optimized. The proposed architecture has advantages such as the following: 1) the input part of the interface channel is designed to have an active gm-c integrator with high-input impedance to remove the necessity of the input buffer; 2) an antialiasing filter can be discarded by efficiently using the CT ΔΣ loop s inherent antialiasing function. The RZ DAC signaling scheme is utilized to reduce the pulse distortion and clock jitter sensitivity of the CT loop. The excess loop delay problem is eliminated by using a

8 520 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 61, NO. 2, FEBRUARY 2012 structure involving a half-cycle delay. The measurement results show a successful chip performance for the ECM interface with a DR of 75 db over a 25-kHz signal bandwidth without any extra input buffer or antialiasing filter. REFERENCES [1] T. Bretterklieber, H. Zang, M. Motz, T. Werth, and D. Hammerschmidt, Versatile sensor front end for low-depth modulation capacitive sensors, in Proc. IEEE Instrum. Meas. Technol. Conf., May 12 15, 2008, pp [2] Q. Jia, X. Li, and G. C. M. Meijer, A precision integrated interface circuit for thermopile based sensors, in Proc. IEEE Instrum. Meas. Technol. Conf., May 12 15, 2008, pp [3] A. Depari, A. Flammini, D. Marioli, E. Sisinni, A. D. Marcellis, G. Ferri, and V. Stornelli, A new and fast-readout interface for resistive chemical sensors, IEEE Trans. Instrum. Meas., vol. 59, no. 5, pp , May [4] L. Bissi, M. Cicioni, P. Placidi, S. Zampolli, I. Elmi, and A. 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Baker, CMOS: Mixed-Signal Circuit Design. New York: Wiley/IEEE Press, [27] ADMP421 Data Sheet, Analog Devices Inc., Norwood, MA, Feb [Online]. Available: Youngkil Choi (S 06) received the B.S. and M.S. degrees in electrical engineering and computer science from Hanyang University, Ansan, Korea, in 2004 and 2006, respectively, where he is currently working toward the Ph.D. degree in electrical engineering and computer science. His research interests include low-power highperformance sigma delta modulators and mixedsignal integrated circuits. Hyungdong Roh (S 06) received the B.S. and M.S. degrees in electrical engineering and computer science from Hanyang University, Ansan, Korea, in 2005 and 2007, respectively, where he is currently working toward the Ph.D. degree. His current research interest is low-voltage and low-power sigma delta analog-to-digital converter. Jeongjin Roh (SM 10) received the B.S. degree in electrical engineering from Hanyang University, Seoul, Korea, in 1990, the M.S. degree in electrical engineering from Pennsylvania State University, University Park, in 1998, and the Ph.D. degree in computer engineering from the University of Texas at Austin, Austin, in From 1990 to 1996, he was with Samsung Electronics, Kiheung, Korea, as a Senior Circuit Designer for several mixed-signal products. From 2000 to 2001, he was with Intel Corporation, Austin, TX, as a Senior Analog Designer for delta sigma data converters. In 2001, he joined the Faculty of Hanyang University, Ansan, Korea. His research interests include oversampled delta sigma converters and power management circuits.