3 rd order Sigma-delta modulator with delayed feed-forward path for low-power applications

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1 3 rd order Sigma-delta modulator with delayed feed-forward path for low-power applications Min-woong Lee, Seong-ik Cho Electronic Engineering Chonbuk National University 567 Baekje-daero, deokjin-gu, Jeonju-si, Jeollabuk-do Republic of Korea Abstract: - This paper proposes an architecture of 3 rd order SDM(Sigma-Delta Modulator) with delayed feedforward path in order to reduce power consumption and area. The proposed SDM improve the architecture of conventional 3 rd order SDM which consists of two integrators. In the proposed architecture, the coefficient values of the first stage are doubled by inserting the delayed feed-forward path into the second stage. Accordingly, compared with the conventional architecture, the capacitor value(c I ) of first integrator is reduced by half. Thus, because the load capacitance of first integrator is the half of original value, the output current of op-amp and the capacitance of integrator in the first stage are reduced by half, respectively. Therefore, the proposed method can optimize the power and chip area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V and input signal of 1Vpp/1KHz, signal bandwidth of 24KHz, sampling frequency of MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is 180uW. Key-Words: - Sigma-delta modulator, Low power, Output current, Delayed feed-forward path, Coefficient, Architecture, Op-amp 1 Introduction Sigma-Delta ADC(Analog to Digital Converter) configured by the SDM(Sigma-Delta Modulator) and digital low-pass filter. The SDM can reduce significantly the quantization noise of signal band through the oversampling and noise shaping, and performs the role of pushing out of the bandwidth the noise with high-frequency component of the input signal. The digital low-pass filter eliminates the noise of frequency component outside the bandwidth also, performs the decimation operation and reduces the oversampled frequency of the SDM as the Nyquist frequency. Through this, output value of the high resolution can be obtained. Thus, the low-voltage, low-power and high-resolution etc. of Sigma-Delta ADC can be determined by various architecture and circuit implementation method of the SDM[1][2]. In this paper, an architecture of 3 rd order SDM(Sigma-Delta Modulator) with delayed feedforward path was proposed in order to reduce power consumption and chip area. The proposed SDM improve the architecture of conventional 3 rd order SDM with CIFB(Cascade of Integrators Feedback) which consists of two integrators by using analog and digital feed-back paths. Compared with the conventional architecture, the proposed architecture reduced the ratio of the sampling capacitor(c S ) and integrator capacitor(c I ) of the first SC(Switched-Capacitor) integrator by half. Thus, the load capacitance of the op-amp in the first stage is reduced by half, and the power consumption and chip area of the first stage are reduced by about half. The organization of the paper is as follows: section 2 provides the proposed architecture of 3 rd order SDM. Section 3 will show the details of the designed SDM in the SC circuit level. In section 4, simulation of the circuit and the results will be reported. Finally, section 5 concludes this paper. 2 Proposed architecture of 3 rd order SDM Fig.1 shows a block diagram of the general architecture of 3 rd order SDM with the CIFB. When the SC SDM was designed by using the architecture of Fig.1, the switches, capacitors and three op-amps are required. ISBN:

2 Recent Advances in Electrical and Electronic Engineering Fig. 3 Block diagram of proposed 3rd order SDM architecture When the coefficients A0, B0 of Fig. 3 and Fig.2 are the same, compared with the architecture of Fig. 2, because the architecture of Fig. 3 reduce the Output of first integrator by the delayed feedforward path C0, the output swing of the first integrator is reduced by half as shown in Fig. 4, and the coefficients A0, B0 of Fig. 3 can be increased by double. Therefore, when Fig. 3 is designed as the SC circuit, the capacitor ratio(cs :CI) of first stage is reduced by half, also the load capacitance of op-amp is reduced by half. As a result, the proposed architecture can reduce the power consumption of op-amp and the area of first integrator by about half. Fig. 1 Block diagram of 3rd order SDM architecture with CIFB In the general architecture of Fig. 1, one integrator configures 2nd order SDM by using the analog and digital feed-back paths and another integrator configures 1st order SDM by using the digital feed-back path. Fig. 2 shows a block diagram of conventional architecture which is configured by connecting the integrators as cascade[3]. The conventional architecture reduced one of the three op-amps that occupy most of the power consumption in the SC SDM. Fig. 2 Block diagram of conventional 3rd order SDM architecture In the conventional architecture of Fig. 2, the values of the coefficients A0, B0 are very small in order to guarantee stable output range. Therefore, when the SDM is designed as the SC circuit, the ratio of sampling capacitor(cs) and integrator capacitor(ci) is increased. This means that the load capacitance of op-amp is increased in the first stage, thus, the power consumption and chip area of SC SDM should be increased. This paper propose an architecture of 3rd order SDM with delayed feed-forward path as shown in Fig. 3 in order to improve the problem of the conventional architecture in Fig. 2. Fig. 4 Output range of integrator in the first stage (1) is the NTF(Noise Transfer Function) of the architecture of Fig 2 and Fig. 3. Because the proposed architecture inserted the delayed feedforward path(c0) in the input signal of conventional architecture, the NTF is not affected. Thus, the NTF of Fig. 2 and Fig. 3 are same, and the added path was affected only the coefficients of STF(Signal Transfer Function). az 3 + ez 2 + fz + g NTF = 3 az + bz 2 + cz + d a =1 b = B3 B1 2 c = B0 A1 + B2 + B1 B4 B3 + 1 d = B4 B2 e = B3 2 f = B2 + B1 + 1 g = B2 ISBN: (1)

3 3 Circuit design 3.1 Modeling In this paper, in order to design the proposed architecture as the SC circuit, firstly the modeling of the proposed architecture performed by using the MATLAB tool[4]. The modeling considered the KT/C noise and non-ideal characteristics of op-amp. Table 1 shows the modeling specification of the proposed SDM and Table 2 shows coefficients of the proposed architecture. Table 1 Modeling specifications Parameter Value Sampling Frequency[MHz] OverSampling Ratio 64 Input[V pp, KHz] 1, 1 Signal Bandwidth[KHz] 0.02~24 Op-amp DC gain[db] 60 GBW[MHz] 15 Slew rate[v/µs] 5 KT/C Capacitance[pF] 0.3 DAC[bit] 1 Table 2 Coefficients of proposed architecture Coefficient A0 A1 B0 B1 Value Coefficient B2 B3 B4 C0 Value Circuit design The SC 3 rd order SDM was designed as shown in Fig. 5, based on the results of the modelling. This architecture is used non-overlapping clock basically, and used CMOS switch in order to reduce charge injection that occurs in the integrator. The delayed analog feed-back paths are configured by using timing of additional four clocks other than nonoverlapping clock, and the delayed digital feed-back paths are configured by using D-F/F in the output of comparator. The 1-bit comparator is composed of only dynamic comparator and latch without pre-amp in order to minimize the power consumption. In the circuit of SC SDM, considering the KT/C noise, the sampling capacitor of the first integrator is determined as 0.3pF, and because of insensitivity to noise, the sampling capacitor of second integrator is determined as 0.1pF. Fig. 5 Circuit of proposed SC 3 rd order SDM 3.3 Op-amp design As shown in Fig. 6, the op-amp of Fig. 5 designed as the architecture of fully differential folded cascade that has high unity gain and don t require the capacitor of the frequency compensation. Fig. 6 Fully differential folded cascade op-amp The op-amp of the fully differential architecture needs CMFB(Common-Mode FeedBack) circuit for stable operation in the reference voltage. The CMFB circuit designed as architecture of simple SC type for low-power consumption. The Op-amps of first integrator and second integrator has the same bandwidth in accordance with the sampling frequency. But the each characteristic and power consumption is different because of the load capacitance difference. The opamps were designed to satisfy the modeling specifications and the performances are summarized in the Table 3. Table 3 Summary of op-amp performance 1 st Op-amp 2 nd Op-amp DC gain[db] GB[MHz] 15(C L =1.5p) 16(C L =2p) Phase Margin[ ] Output range[v pp ] 1 1 Slew rate[v/µs] ISBN:

4 Recent Advances in Electrical and Electronic Engineering Power[µW] 65 characteristic of the op-amp and SC circuit. But the ENOB(Effective Number of Bits) is equal as 14-bits Circuit design of SC integrator The sampling frequency of sensitive first integrator to noise should be large more than the certain value. This means that was increased the load capacitance of the op-amp, also the power consumption of the op-amp increased. Fig. 7(a) is the circuit of traditional SC integrator, and Fig. 7(b) shows the circuit of low-power SC integrator used in the first stage of designed SDM. Because Fig. 7(b) divides the sampling capacitor by half and divided capacitors are connected in parallel, the quantity of charge and KT/C noise are equal to the circuit of Fig 7(a). But the integrator capacitance of Fig 7(b) is reduced by half, and the load capacitance of the op-amp reduced by half[5]. Accordingly, the low-power SC integrator can minimize the power consumption of op-amp. (a) (a) (b) Fig. 8 PSD(Power Spectral Density) result of proposed SDM (a) through MATLAB modeling (b) through spectre simulation Table 4 show the comparison results of the cascade architecture with CIFB of Fig. 1, the conventional SDM architecture of Fig. 2 and the proposed SDM architecture with delayed feedforward path of Fig. 3. And the 1st integrators of each architecture designed by using the low-power SC integrator of Fig. 7(b). The comparison contents are the number of op-amps and the number of total coefficient paths as a whole. And about the 1st opamp with the large sampling capacitor, the comparison contents are the values of coefficient, capacitance, the area of capacitor and the power consumption. The proposed architecture of Fig. 3 can increase the coefficients A0, B0 of Fig. 2 doubly by minimizing the output range of 1st integrator. And when designing SC circuit, this means that can reduce the load capacitance of op-amp by about half. Therefore, in first stage of proposed architecture, the power consumption was reduced from 135uW to 65uW and the area of capacitor was reduced from 7.48um2 to 3.8um2. (b) Fig. 7 (a) Circuit of traditional SC integrator (b) Circuit of low-power SC integrator 4 Simulation results Fig. 8(a) shows result of spectrum analysis by MATLAB modeling of the proposed architecture of Fig. 3, and Fig. 8(b) shows result of spectrum analysis by spectre simulation of the SC 3rd order SDM of Fig. 5. The simulation conditions are 1.8V of supply voltage, 1Vpp/1KHz of input signal and MHz of sampling frequency in the 0.18um CMOS process. Consequently, a SNR(Signal to Noise Ratio) is 90.6dB in MATLAB modelling and the SNR is 88.9dB through the spectre simulation. The error of 1.3dB considers that it caused by non-ideal ISBN:

5 Table 4 Comparison about SDM architecture CIFB SDM Conventional SDM [3] proposed SDM # of OTA # of path st Integrator A0, B Area 7.48um um 2 3.8um 2 Power 135µW 135µW 65µW The low-power SC integrator applied to the 1 st integrator of respective architecture. Also, Table 5 shows comparison about the performance of proposed low-power SC SDM and the other low-power SC SDM with audio frequency bandwidth for the performance verification. Table 5 Low-power SDM performance summary and comparison Reference [7] [8] [9] This Work Process(µm) Supply voltage(v) BW(kHz) SNR(dB) OSR Power(µW) FOM(pJ) Normally, the ADC performance can be compared as FOM(Figure Of Merit) of eq. (2), and the smaller value of the FOM shows the better performance. FOM = 2 ENOB Power 2 BW (2) Accordingly, in this paper, the proposed SDM indicated relatively high performance. 4 Conclusion The conventional architecture reduced integrator from 3 to 2 by using the analog and digital paths, but coefficients of the first integrator become very smaller. This paper proposes the architecture with delayed feed-forward path in order to improve this disadvantage. Compared with the conventional architecture, coefficient values of first integrator in the proposed architecture increased doubly by minimizing output swing of the first integrator. Thus, when proposed architecture designed as the SC circuit, the power consumption and capacitor area of first integrator ware reduced more about half than the conventional architecture. But, the proposed architecture requires additional four clocks other than two non-overlapping clocks when designed as the SC circuit of SDM. Therefore, the performance of SDM degraded because of demand of many switches, complex circuit design and influence of the clock jitter/glitch. In the future, we will study to minimize the number of clock in order to complement these disadvantages. In this paper, implemented SC 3 rd order SDM by using the proposed architecture have resolution of 14-bit and total power consumption of 180uW. Thus, the designed SC 3 rd order SDM may be applied to portable low-power digital products that require the high-resolution and process the audio signal in the low-frequency bandwidth. References: [1] Richard Schreier and Gabor C. Temes, Understanding Delta-Sigma Data Converters, Wiley-IEEE Press, 2005, pp [2] J. Candy and G. Temes, Oversampling methods for A/D and D/A conversion in Oversampling Delta-Sigma Data Converters, IEEE Press, New York, 1992, pp [3] A. Pena-Peres, E. Bonizzoni and F. Maloberti, A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order Σ Modulator, vol.47, no.9, Sep. 2012, pp [4] A. Hamoui, T. Alhajj, and M. Taherzadeh-Sani, Behavioral modeling of opamp gain and dynamic effects for power optimization of deltasigma modulators and pipelined ADCs, in Proc. Int. Symp. Low Power Electron. and Design (ISLPED), Oct. 2006, pp [5] A. Nilchi and D. A. Johns, Charge-pump based switched-capacitor integrator for modulators, Electron. Lett., vol.46, no.6, Mar. 2010, pp [6] Daisuke Kanemoto, Toru Ido and Kenji Taniguchi, A 7.5mW 101dB SNR Low- Power High-Performance Audio Delta-Sigma Modulator Utilizing Opamp Sharing Technique, International SoC Design Conference(ISOCC), 2011, pp [7] L. Liu, D. Li, L. Chen et al, A 1V 663µW 15-bit Audio Σ Modulator in 0.18µm CMOS, IEEE ISBN:

6 Circuits and Systems(ISCAS), 2011, pp [8] H. Park, K. Nam, D. K. Su et al, A 0.7-V 100dB 870-uW Digital Audio CMOS Sigma-Delta Modulator, IEEE J. of Solid-State Circuits, Vol.44, no.4, Apr. 2009, pp [9] X. Gou, Y. Li, J. Chen et al, A Low Power Low Voltage 16 bit Audio Σ Modulator, IEEE Circuits and Systems(ISCAS), 2009, pp ISBN: