MASH 2-1 MULTI-BIT SIGMA-DELTA MODULATOR FOR WLAN L 2 ( ) ( ) 1( 1 1 1

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1 MASH 2- MULTI-BIT SIGMA-DELTA MODULATOR FOR WLAN Yu hang, Ning Xie, Hui Wang and Yejun He College of Information Engineering, Shenzhen University, Shenzhen, Guangdong 58060, China (Ning Xie) (Hui Wang) (Yejun He) Ning Xie National Mobile Communications Research Laboratory, Southeast University, Nanjing, Jiangsu 20096, China ABSTRACT This paper mainly explores how oversampling and feedback can be employed in high-resolution ( Δ) modulators to extend the signal bandwidth into the range of megahertz, where oversampling ratio is constrained. A 2- cascaded multi-bit architecture suitable for broad-band applications is presented, and a linearization technique referred to as partitioned data weighted averaging (DWA) is introduced to suppress in-band digital-to-analog converter (DAC) errors. All blocks implement in the popular MATLAB/SIMULINK environment. The proposed set of blocks also takes into account most of non-ideal factors on sigma-delta modulator. As shown in the experimental results, for a MHz signal bandwidth and -3dBFS input signal, the MASH 2-4-bit sigma-delta modulator can achieve 52.5 db SNDR (signal to noise-and-distortion rate) at a 24Msample/s Nyquist conversion rate with an oversampling ratio of 6. KEY WORDS Sigma-Delta modulator, Cascaded, Multi-bit, DWA, Simulations. INTRODUCTION Because of their outstanding linearity, oversampling converters have become a popular technique for data conversion[]. However, due to the nature of oversampling, these converters are much slower than their Nyquist-rate counterparts. Hence, the application of sigma-delta modulator are usually used to low-speed high-linearity applications such as digital audio. By combining oversampling and feedback to shape the quantization noise, sigma-delta modulators provide an efficient means of exchanging speed for accuracy[2, 3]. In order to improve performace of sigma-delta modulator, we mainly have three techniques: oversampling, noise shaping and multi-bit quantizer. As shown in Eqn.(), SNR[4] can be written as 32L+ SNR 2 2 ( ) 0log0( L 2 B db = OSR ) () 2 π 2L where OSR is oversampling ratio, L is order of modulator and B is the number of bits in quantizer. Obviously, the SNR is determined by L, B, and OSR and for a wide bandwidth application such as WLAN receiver, OSR and L cannot be made higher for the consideration of high sampling frequency, circuit complexity and power dissipation. In the design, an OSR of 6 and L of 3 have been chosen as a trade-off between the sampling frequency and the given bandwidth. Then the resolution B determines the performance of the modulator since OSR and L have been determined. For a wireless communication system, the minimum dynamic range of 50 to 70 db for a MHz bandwidth is required. To reach the required specification, 4-bit quantizers should be used for both stages. This paper is organized as follows: section is the introduction. Section 2 presents single loop sigma-delta modulator. Section 3 designs a MASH 2- multi-bit sigma-delta modulator. The non-ideal factors in modualtor and non-linearities of DAC(digital to analog converter) are respectively discussed in section 4 and section 5. Finally, section 6 concludes the paper. 2. SINGLE LOOP MULTI-BIT SIGMA-DELTA MODULATOR In one form of single-stage modulator that shapes the noise by a multiple-order noise difference, the noise shaping filter consists of a series of integrators nested within multiple feedback loops[2]. The number of integrators in the forward path defines the order of differential noise shaping provided by the modulator. Shown in Fig. is a 2 nd -order multi-bit sigma-delta modulator. In the structure, oversampling and negative feedback are used to shape the spectrum of the quantization noise, moving most of the noise energy to frequency above the signal baseband. Assuming that DAC is ideal, each node of modulator can be written as ( ) ( ) ( ) ( ) ( ) Y 2 2( ) X( ) E( ) ( 2 ) Y = X + E (2) = + (3) where Y( ), Y2( ) are respectively the first integrator and the second integrator output, while X(z) and E() are This work was supported by three National Natural Science Foundations of China (No.60082, No , No ), the Natural Science Foundation of Guangdong, China (No ), the Foundation for Distinguished Young Talents in Higher Education of Guangdong, China (No. LYM0922), two Fundamental Research Programs of Shenzhen City (No.JC A, No.JC A) and the open research fund of National Mobile Communications Research Laboratory, Southeast University.

2 respectively the input signal and the quantization noise. The final output of sigma-delta modulator can be given by ( ) = 2 ( ) + ( )( ) 2 Y X E (4) ( ) 2 where is the 2 nd -order noise transfer function(ntf). Obviously, the quantization noise is shaped by the 2 nd -order filtering function. Y ( ) Y2 ( ) E ( ) Fig.. 2-order single bit sigma-delta modulator However, with the order of single-loop modulator increasing, it will bring stability issues[5]. Once one of integrators output is high, the input to quantizer will be high, which will result in quantizer overload and modulator performance degradation. In order to solve overloading issues, we will employ cascaded achitechture of sigma-delta modulator. 3. DESIGN OF 2- CASCADED 4-BIT SIGMA-DELTA MODULATOR Corresponding to a single-loop sigma-delta modulator is cascaded or MASH(multi-stage noise shaping) sigma-delta modulator. For a given oversampling ratio, the resolution of sigma-delta modulator can be increased by increasing the order of the noise shaping. This can be accomplished, without concern for stability, by cascading several modulator stages, each of which combines a single quantizer with first or second order noise shaping. As shown in Fig.2, it consists of two low-order modulator and a digital cancellation logic circuit. Using st -order or 2 nd -order in ecch stage in modulator, it can avoid instability issues caused by high order modulation[3]. E Y E 2 Y 2 Fig.2. MASH 2- multi-bit sigma-delta modulator In the MASH achitecture, the next stage only processes quantization noise from the last stage and then offset the last stage quantization noise by digital noise cancellation logic. So the final output from modulator only contains input signal and the final stage quantization noise which suffers from high order noise shaping. Its noise shaping order is equal to the number of integrators in the sigma-delta modulator. From Fig.2 we can also see that the first stage is a 2 nd -order modulator and the second stage is a st -order modulator. The output of both stages can be respectively written as where Y( ), Y2( ) are respectively the output of the ( ) = ( ) 2 + ( )( ) 2 Y X E ( ) ( ) ( )( ) Y2 = E + E2 (6) st -stage and 2 nd -stage, X ( ) is the input signal and E( ), E ( ) 2 are respectively quantization noise from the st -stage and the 2 nd -stage. In order to offset the quantization noise from the st -stage, transfer functions of noise cancellation logic can be written as Y( ) = Y( ) H( ) + Y2( ) H2( ) (7) where H( ), H2( ) are respectively the first stage and the second stage digital circuit transfer functions. We assume that ( ) =, ( ) = ( ) 2 H H 2 from Eqn.(6),(7),(8),(9), the final output of modulator Y(z) can be given by (5) (8)

3 ( ) = 3 ( ) + ( )( ) 3 Y X E2 From equation (0), we can see that the output signal of modulator only contains of input signal X() without any attenuation and the second stage quantization noise E 2 ( ) with 3 rd -order noise shaping. However, the first stage quantization noise E ( ) has been offset by the digital cancellation logic. Simulation results show that when the input signal level is -3dBFS, bandwidth is MHz, 6 times oversampling ratio in the case, the SNDR up to 78.2dB, as shown in Fig.3. (9) Fig.3 PSD of ideal MASH 2-4-bit sigma-delta modulator 4. NON-IDEALITIES FOR SIGMA-DELTA ADC Cascaded switched-capacitor implementation of the modulator, in addition to quantization noise, there are many non-ideal factors[6] and sources of error limit the performance of sigma-delta modulator. A. Clock Jitter The error introduced when a sinusoidal signal with amplitude A and frequency f in is sampled at an instant[6] which is in error by an amount δ us given by Eqn.(0) can be expressed by fig.4 d x( t+ δ) xt ( ) 2πfinδAcos( 2πfint) = δ x() t (0) dt Fig.4 Modeling clock jitter B. Integrator Noise Because of the large low-frequency gain of the first Integrator, the integrator noise mainly contains thermal noise(kt/c) associated to the sampling switches and the intrinsic noise of the operational amplifier[6]. Simulink models of KT/C noise and Op-Amp noise are respectively shown in Fig.5, Fig.6. Fig.5 Modeling switches thermal noise(kt/c noise) Fig.6 Op-Amp noise C. Integrator Non-Idealities The non-ideal effect is a consequence of the op-amp non-idealities, namely finite gain and bandwidth, slew rate and saturation voltages[6]. These will be shown in Fig.7.

4 Fig.7 Modeling real integrator Alfa( α ) is the factor of leakage. The transfer function of integrator with leakage becomes: ( ) H = α () So the dc gian can be given by H = (2) 0 α The limited gain at low-frequencies increases the in-band noise. Using the saturation block inside the feedback loop of integrator is to avoid quantizer overloading. From the above discussion, the non-ideal simulink model of MASH 2- sigma-delta modulator is shown in Fig.8. According to parameters of tabe, simulation result shows that for a MHz signal bandwidth, the non-ideal MASH 2-4-bit sigma-delta modulator can achieve 46.5-dB SNDR at a 24-Msample/s Nyquist conversion rate with an oversampling ratio of 6, as shown in Fig.9. Fig.8 Non-ideal simulink model of MASH 2- modulator Fig.9 PSD of non-ideal MASH 2-4-bit sigma-delta modulator Table. simulation parameters for non-idealities Modulator Coefficient setup parameter Boltzmann constant.38e-23 Absolute 300 temperature Thermal noise Cs=3.2 pf Sampling jitter 4 ps Op-amp finite gain (e3-)/e3 Op-amp slew rate 0e6 V/s Op-amp GBW 50 MHz 5. DWA FOR MULTI-BIT DAC Good attenuation of DAC noise due to component mismatch is provided by the data-weighted averaging(dwa) algorithm[7], which can achieve first-order DAC noise shaping[7]. In DWA algorithms, the DAC output value is the sum of unit DAC elements that are chosen cyclically. Cyclical selection ensures that the mismatch error is averaged out as fast as possible, as shown in Fig.0.

5 X () = 3 X (2) = 2 X (3) = 5 X (4) = 3 X (5) = 2 X (6) = 3 Unit caps Fig.0 Theory for DWA Add DWA algorithm to the multi-bit DAC, we can attain an improved MASH 2- multi-bit sigma-delta modulator with DWA, as shown in Fig.. The DWA algorithm realizes DAC mismatch shaping transfer function of the form [7]. So the final output of modulator can be given by E Where d ( ) is the multi-bit DAC mismatch error. 3 3 Y X E E d ( ) = ( ) + ( ) ( ) + ( ) ( ) (3) Fig. Simulink model of MASH 2- multi-bit sigma-delta modulator with DWA Simulation result reveals that the DWA algorithm with the MASH 2-4-bit sigma-delta modulator can achieve nearly perfect first-order DAC noise shaping in the baseband and on the average, 6dB improved SNDR, as shown in Fig.2. Fig.2 Comparison between DWA and NON-DWA for 2-cascaded 4-bit sigma-delta modulator 6. CONCLUSION Cascaded sigma-delta modulators offer a method of achieving high-resolution A/D conversion without the stability problems associated with modulators that embed a third or higher order noise shaping filter and a single quantizer within one or more nested feedback loops. In this paper, based on MATLAB/SIMULINK tools the behavioral model of MASH 2- modulator is constructed, the proposed sigma-delta modulator can achieve 52.5-dB SNDR at a 24-Msample/s Nyquist conversion rate with an oversampling ratio of 6. It can be seen that the modulator model above mentioned is effective[6], which also can be used for analysis on the structure performance of sigma-delta modulator. REFERENCES [] G. C. Temes and J. C. Candy, "A tutorial discussion of the oversampling method for A/D and D/A conversion," in Circuits and Systems, 990., IEEE International Symposium on, 990, pp vol.2. [2] J. Candy, "A Use of Double Integration in Sigma Delta Modulation," Communications, IEEE Transactions on, vol. 33, pp , 985. [3] B. E. Boser and B. A. Wooley, "The design of sigma-delta modulation analog-to-digital converters," Solid-State Circuits, IEEE Journal of, vol. 23, pp , 988. [4] K. L. Wei Li, Liang Wang, "Design of 6-bit Third Order Cascaded Sigma-Delta Modulator," MODERN ELECTRONICS TECHNIQUE, 200. [5] M. Yagyu and A. Nishihara, "Fast and efficient algorithm to design noise-shaping FIR filters for high-order overload-free stable sigma-delta modulators," in Circuits and Systems, ISCAS '04. Proceedings of the 2004 International Symposium on, 2004, pp. I Vol.. [6] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto, and F. Maloberti, "Modeling sigma-delta modulator non-idealities in SIMULINK(R)," in Circuits and Systems, 999. ISCAS '99. Proceedings of the 999 IEEE International Symposium on, 999, pp vol.2.

6 [7] R. T. Baird and T. S. Fiez, "Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 42, pp , 995.

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