Low-Complexity High-Order Vector-Based Mismatch Shaping in Multibit ΔΣ ADCs Nan Sun, Member, IEEE, and Peiyan Cao, Student Member, IEEE

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1 872 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 58, NO. 12, DECEMBER 2011 Low-Complexity High-Order Vector-Based Mismatch Shaping in Multibit ΔΣ ADCs Nan Sun, Member, IEEE, and Peiyan Cao, Student Member, IEEE Abstract This paper presents a new vector-based mismatchshaping technique for multibit ΔΣ analog-to-digital converters. It has low hardware complexity, which only linearly grows with the number of unit digital-to-analog converter elements. Compared with the existing low-complexity vector-based technique, this technique does not require extra filters and has much better mismatch-shaping effect and stability. Simulations under various conditions prove its validity. Index Terms Data converter, mismatch shaping, ΔΣ analogto-digital converter (ADC). Fig. 1. Architecture of a multibit ΔΣ ADC with mismatch shaping. I. INTRODUCTION A MULTIBIT ΔΣ analog-to-digital converter (ADC) is more advantageous than its 1-bit counterpart, for the quantization noise is smaller and the noise transfer function (NTF) can be more aggressive, both of which lead to a much higher theoretical signal-to-noise ratio (SNR). The relative drawback of a multibit ΔΣ ADC is that its internal multibit digital-to-analog converter (DAC) is not intrinsically linear due to element mismatches. As a result, the noise caused by DAC mismatches, unshaped by the NTF, limits the overall SNR. To address this issue, researchers have developed various mismatch-shaping techniques [1] [19]. The basic idea is to insert an element selection logic (ESL) block that converts a multibit quantizer output d[n] to a selection vector sv[n] that drives a unit-element DAC (see Fig. 1). The ESL block is specially designed so that each element of sv[n] has a shaped spectrum, and thus, the noise due to mismatches is always shaped regardless of the magnitude and the distribution of the mismatches. The cost of using mismatch shaping is twofold: 1) the ESL block occupies extra chip area and dissipates power; and 2) the propagation delay through the ESL block eats up the overall ΣΔ loop-delay budget, requiring faster settling and leading to a further increased power dissipation. 1 Manuscript received May 6, 2011; revised July 11, 2011 and September 4, 2011; accepted October 10, Date of publication November 28, 2011; date of current version December 14, This paper was recommended by Associate Editor E. Bonizzoni. N. Sun is with the Department of Electrical Engineering, The University of Texas at Austin, Austin, TX USA. P. Cao is with the Department of Electrical Engineering, Cornell University, Ithaca, NY USA. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCSII The delay of the ESL block decreases as technology advances due to its digital nature, but it is still an issue for high clock-rate applications. For example, a 200-ps delay would require the loop to settle 20% faster for a 1-GS/s converter. Fig. 2. Mismatch-shaping architecture of a standard vector-based technique. Among existing mismatch-shaping techniques, [1] [7] provide the first-order shaping, and [8] [19] provide higher order ( 2) shaping. Compared with the first-order shaping, higher order shaping provides a higher SNR and suffers much less from spurious tones [10]; however, its corresponding ESL block is more complicated and/or has a longer propagation delay. To understand this issue more clearly, let us take a close look at one widely used second-order mismatch-shaping technique the vector-based technique of [13] [18]. Its basic structure for the ESL block is shown in Fig. 2. It resembles the standard ΔΣ modulator but with two major differences: 1) the state variables (e.g., x[n] and y[n]) are vectors with the length of N; and 2) the quantizer is a vector quantizer consisting of a sorter and an array of comparators. The advantage of the vector-based approach is its short propagation delay. There is only one comparator delay from d[n] to sv[n] ( y[n] is ready in the previous clock cycle and, hence, does not cause any delay). 2 As a result, the vectorbased approach suits well for high sampling rate applications. The drawback of the vector-based approach is its high hardware complexity. The sorter, which sorts N variables at high speed, requires intensive hardware, whose complexity quadratically grows with N. To reduce the complexity of the sorter, Yasuda et al. [17] exploited the fact that the vector-based method does not necessarily need a complete sorting of all N elements and used a partial sorter in a modified architecture, 2 Here, d[n] is assumed to be binary. If d[n] is thermometer coded, the total delay is one comparator delay plus one thermometer-to-binary converter delay /$ IEEE

2 SUN AND CAO: HIGH-ORDER VECTOR-BASED MISMATCH SHAPING IN MULTIBIT ΔΣ ADCS 873 TABLE I COMPARISON BETWEEN DIFFERENT SECOND-ORDER MISMATCH-SHAPING TECHNIQUES Fig. 3. Mismatch-shaping architecture of [17]. which leads to overall ESL block complexity only linearly growing with N. Nevertheless, there are three drawbacks for the technique of [17]. 1) It requires N 1 additional filters. These extra filters occupy chip area and dissipate power. 2) Both the mismatch-shaping effect and the stability are worsened. Compared with the standard vector-based method with the complete sorting, the noise floor for [17] is 20 db higher for N =8. Our simulations also show that the technique of [17] is unstable for N 16. 3) Its partial sorter can only provide accurate sorting among two neighboring elements, leading to large vector quantization noise. 3 This paper proposes a new low-complexity vector-based mismatch-shaping technique. It addresses the three aforementioned problems of [17]. It does not require additional filters and substantially improves the mismatch-shaping effect and the stability through the design of a new filter and a new partial sorter. As shown in Table I, which summarizes the properties of various vector-based methods, our technique represents an overall better tradeoff among hardware complexity, mismatchshaping effect, and stability. II. REVIEW OF THE TECHNIQUE OF [17] Before we explain our algorithm, let us take a look at the technique of [17], whose architecture is in Fig. 3. Its central idea is to partially sort the filter output using a simple sorter consisting of N 1 comparators. To allow the global comparisons between all elements, an adder tree consisting of N 2 adders is used to calculate the summations of adjacent elements of sv[n], which are sent to extra filters and the partial sorter. It is easy to prove that this architecture shapes the mismatch noise as long as the feedback loop is stable. Compared with the standard vector-based technique [14] [16], the advantage of [17] is its low hardware complexity, 3 The vector quantization noise is defined as the difference between the input ( x[n]) and the output ( sv[n]) of a vector quantizer. Fig. 4. Block diagram for the third-order ΔΣ ADC. Fig. 5. Output spectra for the standard vector-based technique of [14] [16] and the technique of [17]. which only linearly grows with N; however, the price to pay is that it requires extra filters, which are hardware intensive, particularly for high mismatch-shaping orders. Furthermore, since the sorting is incomplete, both the mismatch-shaping effect and the stability are undermined. More specifically, we simulated the standard vector-based technique of [14] [16] and the technique of [17] for a third-order ΔΣ ADC, whose block diagram is in Fig. 4 and coefficients are a 1 =0.61, a 2 = 2.03, and a 3 =2.36 (the same model is used in all following simulations). The oversampling ratio is 64, the input amplitude is 3-dB full scale, and the element mismatch is normally distributed with a 1% standard deviation. Fig. 5 shows the output spectra. For N =8, the feedback loop of [17] is stable, and the mismatch noise is second-order shaped, but its noise floor is more than 20 db higher than that of the standard vectorbased technique [14] [16]. For N =16, the feedback loop of [17] is unstable, and the mismatch noise is not shaped.

3 874 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 58, NO. 12, DECEMBER 2011 Fig. 6. Our new mismatch-shaping architecture. Fig. 8. Block diagram of (a) the conventional filter and (b) our new filter. Fig. 9. Frequency responses of H MNTF (z) and H MNTF (z). Fig. 7. Connections and schematics for the adder tree and the partial sorter. III. OUR MISMATCH-SHAPING TECHNIQUE Our technique builds upon [17] but with key improvements that address the aforementioned issues of [17]. Extra filters are removed by using a new architecture. The mismatch-shaping effect and the stability are substantially improved through the design of a new filter and a new partial sorter. A. New Architecture Without Extra Filters Fig. 6 shows our new mismatch-shaping architecture, in which we eliminate extra filters by moving the adder tree to filter outputs. The selection patterns for this architecture and the architecture of [17] are identical because filtering is a linear operation: calculating summations first and then filtering results, which the technique of [17] does, is equivalent to filtering inputs first and then performing summations, which our technique does. The advantage of our approach is that we do not need extra filters to process the summation results. This way, we reduce the total number of filters by almost 50% without paying any cost. Note that this filter reduction has been briefly mentioned in [18], but no detail is provided. In addition, it is not implemented in [17], which is published after [18] by the same authors. Fig. 7 shows the schematics for the adder tree and the partial sorter for N =8. This partial sorter, which was adopted from [17], contains N 1 comparators. Section III-C will present a new partial sorter that allows a more complete sorting while maintaining low hardware complexity. B. New Filter One key to the improvement of the mismatch-shaping effect and the stability is the design of a new filter. The block diagram of the conventional second-order filter used in standard vectorbased techniques of [14] [18] is shown in Fig. 8(a). 4 Its transfer function is given by F (z) = (2 z 1 )z 1 (1 z 1 ) 2. (1) Using a simple linear model for the vector quantizer, the mismatch NTF (MNTF) for the feedback loops (see Figs. 2, 3, and 6) can be obtained as follows: H NTF (z) = 1 1+F (z) =(1 z 1 ) 2 (2) which shows that the mismatch noise is shaped to the second order [14]. Its frequency response is plotted in Fig. 9. Its low-frequency gain is small, but its high-frequency gain is greater than 1. Having a large gain at high frequencies is fine for standard vector-based algorithms of [14] [16] because their vector quantization noise is relatively small due to the complete sorting; however, it is problematic for the technique of [17] using a partial sorter because its vector quantization noise is much larger, and hence, providing a large gain at high frequencies may cause instability (see Fig. 5). 4 To hold vector variables bounded, we need to modify the z 1 /(1 z 1 ) blocks in Fig. 8 to subtract the minimum element of a vector. Please refer to Fig. 4 of [13] for details. Here, we omit them for simplicity of presentation.

4 SUN AND CAO: HIGH-ORDER VECTOR-BASED MISMATCH SHAPING IN MULTIBIT ΔΣ ADCS 875 Fig. 10. Output spectra with the new filter. To reduce the high-frequency gain while maintaining the noise shaping at low frequencies, we increase the feedforward path gain from 2 to 8, as shown in Fig. 8(b). Its corresponding transfer function is changed to 5 ( ) F (z)=8 z 1 z z z 1 = (8 7z 1 )z 1 (1 z 1 ) 2 (3) and its corresponding MNTF, i.e., HMNTF (z), is given by H MNTF(z) = 1 1+F (z) = (1 z 1 ) 2 1+6z 1 6z 2 (4) Fig. 11. Schematics for the new partial sorter and the adder tree. whose frequency response is also plotted in Fig. 9. At low frequencies, H MNTF (z) and HMNTF (z) are almost identical, but at high frequencies, HMNTF (z) is 20 db lower than H MNTF (z), which leads to improved stability according to [20]. The output spectra for this new filter are shown in Fig. 10. As compared with Fig. 5 for [17], the use of the new filter lowers the noise floor by more than 15 db for N =8 and stabilizes the loop for N =16. The improved stability leads to a smaller swing at the output of the filter. For example, for N = 8, the output swing for the conventional filter is 60, whereas that for the new filter is only 22. Note that the feedforward gain of 8 can be further increased to enhance the stability, but it is not necessary because the loop is already stabilized. We chose 8 for its simplicity of implementation multiplication by 8 is just shifting 3 bits. There is another more qualitative way to understand why having an increased feedforward gain improves stability. F (z) of (3) can be considered as a pure first-order filter plus a pure second-order filter. The feedforward gain represents the relative ratio between them. If the feedforward gain goes to infinity, F (z) would reduce to a first-order filter, which is unconditionally stable. Therefore, increasing the feedforward gain tends to make the filter behave more like a first-order filter and, hence, leads to improved stability. 5 This new filter does not increase the magnitude of the vector quantization noise, which is observed through simulation. Fig. 12. Schematic for the complete sorter for four elements. C. New Low-Complexity Partial Sorter Despite the substantial improvement due to the new filter, the mismatch-shaping effect for the partial sorter is still 8 db worse than that for the complete sorter (see Figs. 5 and 10) because the incomplete sorting causes larger vector quantization noise. To further reduce noise, we want a new partial sorter that sorts more completely than that in Fig. 7. To this end, we devise a new partial sorter shown in Fig. 11 for N =8. It uses two complete four-element sorters, whose schematic is in Fig. 12. y[n] in Fig. 11 corresponds to the ranks of x[n]. For example, if x i [n] = max{ x[n]} and x j [n] = min{ x[n]}, then y i [n] =7and y j [n] =0. Compared with the old partial sorter in Fig. 7 that can only provide accurate sorting among two neighboring elements, the new partial sorter in Fig. 11 provides accurate sorting among four neighboring elements. As a result, the output of this new partial sorter more closely resembles that of the complete sorter, and hence, the

5 876 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 58, NO. 12, DECEMBER 2011 IV. CONCLUSION This paper has reported a new low-complexity vectorbased mismatch-shaping technique. Three key improvements were proposed to address the drawbacks of the existing lowcomplexity approach of [17]. The proposed technique, with the new architecture, the new filter, and the new partial sorter, favorably compares with other high-order ( 2) vectorbased mismatch-shaping algorithms considering hardware cost, mismatch-shaping effect, and stability. Fig. 13. Output spectra for various filter and sorter configurations. TABLE II SNR AND HARDWARE COMPLEXITY COMPARISONS noise is smaller. This structure for the new partial sorter can be easily generalized for any N =2 m (m N), containing 7N/4 1 comparators and 2N 2 adders. For example, for N =16, we use four 4-element sorters to sort x 1 x 4, x 5 x 8, x 9 x 12, and x 13 x 16 and use three comparators to compare 4 i=1 x i with 8 i=5 x i, 12 i=9 x i with 16 i=13 x i, and 8 i=1 x i with 16 i=9 x i. Fig. 13 and Table II show the output spectra, SNRs, and hardware complexity for various vector-based mismatch-shaping techniques with different sorter and filter configurations. The case with the complete sorter corresponds to the standard vector-based technique of [14] [16], and the case with the old partial sorter and the old filter corresponds to the technique of [17]. Our technique with the new partial sorter and the new filter represents a better tradeoff: our SNR is 47 db higher than that of [17], with similar hardware complexity of O(N), and is only 3 db lower than that of [14] [16], whose complexity grows with O(N 2 ). REFERENCES [1] B. H. Leung and S. Sutarja, Multibit σ δ A/D converter incorporating a novel class of dynamic element matching techniques, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 1, pp , Jan [2] H. S. Jackson, Circuit and method for cancelling nonlinearity error associated with component value mismatches in a data converter, U.S. Patent , Jun. 22, [3] R. W. Adams and T. W. Kwan, Data-directed scrambler for multi-bit noise shaping D/A converters,, US Patent , Apr. 4, [4] R. T. Baird and T. S. Fiez, Linearity enhancement of multi-bit ΣΔ A/D and D/A converters using data weighted averaging, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 12, pp , Dec [5] K. D. Chen and T. H. Kuo, An improved technique for reducing baseband tones in sigma delta modulators employing data weighted averaging algorithm without adding dither, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 1, pp , Jan [6] A. A. Hamoui and K. W. Martin, High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broadband applications, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp , Jan [7] H.-Y. Hsieh and L. Lin, A first-order tree-structured DAC with reduced signal-band noise, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 5, pp , May [8] R. K. Henderson and O. J. A. P. Nys, Dynamic element matching techniques with arbitrary noise shaping functions, in Proc. IEEE Int. Symp. Circuits Syst., May 1996, pp [9] A. Keady and C. Lyden, Tree structure for mismatch noise-shaping multibit DAC, Electron. Lett., vol.33,no.17,pp ,Aug [10] I. Galton, Spectral shaping of circuit errors in digital-to-analog converters, IEEE Trans. Circuits Syst. II, Analog Digit Signal Process., vol. 44, no. 10, pp , Oct [11] E. Fogleman, J. Welz, and I. Galton, An audio ADC delta sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC, IEEE J. Solid-State Circuits, vol. 36, no. 3, pp , Mar [12] J. Welz, I. Galton, and E. Fogleman, Simplified logic for first-order and second-order mismatch-shaping digital-to-analog converters, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 11, pp , Nov [13] N. Sun, High-order mismatch shaping in multibit ΔΣ DAC, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 6, pp , Jun [14] R. Schreier and B. Zhang, Noise-shaped multibit D/A convertor employing unit elements, Electron. Lett., vol. 31, no. 20, pp , Sep [15] R. Schreier, Mismatch-shaping digital-to-analog conversion, in Proc. 103rd Convention Audio Eng. Soc., Sep [16] T. Shui, R. Schreier, and F. Hudson, Mismatch shaping for a currentmode multibit delta sigma DAC, IEEE J. Solid-State Circuits, vol. 34, no. 3, pp , Mar [17] A. Yasuda, H. Tanimoto, and T. Iida, A third-order Δ Σ modulator using second-order noise-shaping dynamic element matching, IEEE J. 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