DAC Mismatching Compensation in Multibit Sigma-Delta Modulators with Two-Step Quantization

Transcription

1 DA Mismatching ompensation in Multibit Sigma-Delta Modulators with Two-Step Quantization Sakineh Jahangirzadeh Department of Electrical Engineering, Shahid hamran University of Ahvaz, Ahvaz, Iran Ebrahim arshidi Department of Electrical Engineering, Shahid hamran University of Ahvaz, Ahvaz, Iran Tel: Abstract The use of multibit quantizers in sigma-delta modulators can increase SNR, improve stability and reduce integrator power consumption. However, using multibit quantizers causes nonlinearity in DA converter. In recent decades the uses of data weighted averaging (DWA) methode has been proposed for reducing mismatch errors. However, each added bit to quantizer resolution causes an exponential increase in the power dissipation, required area and complexity of the DWA circuit required to attenuate DA mismatch errors. This paper proposes the prospect of using a segmented feedback path with coarse and fine signals to reduce DWA complexity for modulators with large internal quantizers. This reduces the DWA circuit complexity, power dissipation, and size. But this method adds an additional noise to system. To overcome this problem, two solutions are suggested: one that uses calibration method to cancel mismatch between coarse and fine DAs, and another that frequency-shapes this mismatch error using requantization method. Keywords: Sigma-Delta modulator, Data Wighted Averaging (DWA), Segmentation 1. Introduction The sigma-delta analog to digital modulator (Σ AD) has been widely used in recent decades for low frequency, high resolution applications such as digital audio and high-precision instrumentation [1]. Recently, however, is extending the signal bandwidths of Σ ADs into the MHz range while maintaining high resolution [3]. Three of the key design parameters that affect the resolution of a Σ AD are: the sampling frequency relative to the bandwith of interest (OSR), the order of the noise transfer function, and the number of internal quantization levels. As each is increased, the theoretical resolution of the AD is increased. However, the complexity, power dissipation, and required chip area also increase. Early Σ converter used a single bit quantizer in the loop because of their suitability for VLSI implementation and their superior linearity [4],[5]. The use of multibit quantization has been limited because non linearity in the DA of a sigma-delta modulator translates directly into non linearity of the entire modulator, producing a distorted output. Non linearity in the DA also modulates the quantization noise into the signal band, thus degrading the SNR. However, multibit modulators have several advantages such as increased resolution for the same oversampling ratio, improved stability, relaxed amplifier requirements and better tone behaviour [1]. Attempts to eliminate the non linearity problem associated with multibit Σ modulators have resulted in the use of DWA techniques which 32 SSDR@SIENEREORD.OM

2 shape the noise generated by DA unit element mismatch, shifting it to higher frequencies which are out of the band of interest. Increasing internal quantization levels beyond five bits improves SNR but presents significant challenges. Both the internal quantizer and the DWA logic grow exponentially in complexity, size, and power dissipation as the internal quantizer resolution increases. Using two-step AD is a logical alternative for reducing quantizer power. A folding AD could provide quantization above eight bits while still maintaining the low latency required of the internal quantizer. Recent work has also shown that it is possible to incorporate two-step ADs with in asingle loop modulator, permitting lower power quantizers while maintaining loop stability [6], [7]. This paper will present two architectures that permit the uses of DWA with two step quantizer. The paper is organized as follows. In section 2, basic principle of the data weighted averaging algorithm is presented. In section 3, the problems associated with applying traditional DWA algorithm to a segmented coarse/fine DA structure are discussed. In section 4, calibration method and requantization method in section 5 to overcome these problems are proposed. Simulation results are presented and discussed in section 6,and concluding remarks are provided in section 7. beginning with the next available unused element. The operation principle is illustrated in igure 2. V(n) denotes the DA input at clock cycle n. In the 1st clock four unit elements are selected. Then in the next clock the elements are selected from the first unused, that is the 5th element. If the last element is selected, DWA will start to select the 1st one again. DWA shapes the nonlinear errors with the first-order transfer function (1-z -1 ) [ 8],[11]. 3. DWA With Segmented Quantizer A two-step architecture for the internal quantizercan solve some of the problems arising igure 1. Block diagram of the data weighted averaging (DWA) method 2. The Data Weighted Averaging (DWA) Algorithm Multi bit quantization improves the stability and the signal to quantization noise performance of sigma-delta converters, but it also necessitates the use of dynamic element matching (DEM) to filter the nonlinearity error in the signal band. Data weighted averaging (DWA) is the most widely used DEM algorithms, due to its simplicity and low hardware overhead. igure 1 shows block diagram of the data weighted averaging (DWA) method. The basic concept of DWA is to guarantee that each of the elements is used with equal probability for each digital input code. This is realized by sequentially selecting elements, igure 2. The DWA operation principle 33 SSDR@SIENEREORD.OM

3 from increasing the internal quantization levels beyond five bits. Since these architectures provide the digital data in two sections, coarse bits and fine bits, a logical way to interface with the DWA is to simply perform DWA independently on the coarse and fine DA banks, as illustrated in igure 3. The quantizer produces N bits as the coarse signal and N bits as the fine signal, for a total of N bits (N = N +N ). igure 4 shows a mathematical representation of the segmented architecture from igure 3. The two-step quantizer resolves the N coarse bits, and then subtracts this value from the input and generates the N fine bits from this signal. ( N N ) The gain of 2 inside the quantizer represents a binary right shift to insure the correct place value of the bits, since the coarse bits are the N most significant bits of an N bit signal. Since DWA shapes the error due mismatch unit element DA with first order transfer function, the DWA blocks can be represented as (1-z -1 ), as seen in igure 4. The coarse and fine outputs are each applied to separate DAs using smaller, independent DWA circuits, reducing DWA complexity significantly. The coarse DA transfer function is weighted by ( N N ) 2 times that of the fine DA to insure that the original place values are preserved. However, since this weighting depends on the size of the unit elements involved, a gain mismatch, 1-ε, will be present. The quantization noise, Q, present in both signals Y and Y, ideally will cancel when the coarse and fine signals are summed together at the modulator input. This result be the same as if a single DWA circuit with a single DA had been in the feedback path. However, because of the gain mismatch between the DAs, the coarse quantization error will not completely cancel igure 3. Block diagram of segmentated Σ AD igure 4. Mathematical Block Diagram of Segmented Σ AD and will be transmitted to the output. When the coarse and fine signals are summed together, the quantization noise will not completely cancel while in the single-path method would completely cancel because of gain mismatch between the coarse and fine DA banks in the segmented method. The non-canceled portion of the quantization noise will be added directly to the input signal, and thus be transmitted to the output of the ΣΔ AD. The output, Y, of the ΣΔ AD in igure 4 can be written as : N N Y Y.2 c Y (1) 34 SSDR@SIENEREORD.OM

4 where 2 Y (2) Y ( NN ) [ Q ( X( z) (1 Z 1(1 )( 1Z ) H( z) ) Y ) H( z)] Q Q (3) by substituting (2) and (3) into (1), it is obtained as follows : X H Y 1 (1 )(1 z ) H Q 1 (1 )(1 z ) H (1 z )( Q Q ) H 1 (1 )(1 z ) H (4) or comparison, a single-path approach would lead to: X H Y 1 (1 z ) H Q( z) 1 (1 z ) H (5) A comparsion of equations (4) and (5) show that the segmented system has error term ε (Q Q )(1-z -1 ) present in addition to normal quantization noise. The value of the mismatch term, ε, changes with each clock cycle due to the operation of the DWA. or realistic unit-element mismatch values, ε is small, but still large enough to significantly affect the SNR of the system. 4. alibration Method The mismatch term, ε, from equation (4) represents the deviation from the desired gain ratio of the coarse and fine DAs. Each DA s gain changes with every cycle due to the DWA operation. However, since ΣΔ ADs use oversampling, the average gain of the DA over time is more important than any instantaneous value. So the mismatch, ε from equation (4) can be reduced by matching the average element values between DAs with the ratio of 2 N-Nc : 1. The individual DA element values are not important, as long as the average element values meet this ratio. In an attempt to measure and match the average element values between coarse and fine DAs, a start-up calibration procedure can be used as shown in igure 5. During calibration, the connections from the coarse/fine AD to the feedback path are broken and a single-bit path provides the modulator feedback. A one-bit quantizer is used because it is immune to the mismatch that plagues multi-bit quantizers. The modulator input is grounded and a fixed, D test signal is presented to the coarse and fine DAs through the DWA circuitry. The output is sent to an averaging synck filter, and then measured for each DA individually, with the other DAs disconnected from the circuit. The relative measurement between coarse and fine DA banks can then be used to make the necessary adjustment to match the ratio of the average DA element values. These individual measurements are then compared and used to calculate how much a single fine element must be adjusted to insure an average element size ratio of 2 N-Nc : 1. A distinct advantage of the calibration method is the low complexity of the feedback path. or an 8-bit quantizer, two independent, 4-bit DWA implementations are required. Thus both the complexity and the timing delay of the digital feedback path are minimal. igure 5. Block diagram of calibration method 35 SSDR@SIENEREORD.OM

5 5. The Noise-Shaped Requantization (ReQ) Method The mismatch error between coarse and fine banks can be noise shaped if the coarse quantization is performed within a digital Σ modulator. This method was initially proposed in [9] for a Σ DA, then this method in [10] was proposed for Σ AD along DEM with gain of unity. This paper extends this concept to Σ ADs with DWA algorithm. The basic idea is to generate a new coarse signal with a digital Σ modulator and use this coarse signal to generate a new fine signal. This insures that both the coarse and fine signals are individually noise shaped, which is performed in a way that causes the quantization error leakage to be noise shaped as well. Even though it does not completely cancel errors due to DA mismatch, the quantization error noise power will be outside the signal band. The process is modeled in igure 6. igure 7 shows a mathematical representation of the ReQ architecture from igure 6. The digital coarse and fine signals from the quantizer are first concatenated to form an N-bit signal. This signal is then requantized to N bits using a digital first-order Σ modulator. Then coarse signal is subtracted from the original N-bit signal to form the new fine signal, comprised of N +1 bits. After requantization, the new coarse and fine signals become: ( N N ) Y 2 [ Y Q (1 z )] (6) igure 6. Block diagram for REQ method igure 7. Mathamatical block diagram of REQ method noise-shaped away from the signal band. The output of the system with ReQ as in igure 7 is derived as follows: Y Q (1 z ) (7) Y ' Yc( z).2 N N Y (8) Signals Y' (z) and Y' (z) then pass through independent DWA blocks and DAs and are summed at the input of the modulator. With first-order requantization (ReQ), the quantization error that is not completely cancelled due to coarse/fine DA mismatch as in Equation (4) is where ( N N) Y 2 [ Q ( X N N (1 )(1 z )2. Y (9) Y (1 z )) H ] 36 SSDR@SIENEREORD.OM

6 Science Series Data Report Vol 4, No. 5;May 2012 and Y ( z ) Q ( z ) Q ( z ) (10) by substituting (9) and (10) into (8), it is obtained as follow: Y ' X H 1 (1 )(1 z 1 ) H ( z ) Q 1 (1 )(1 z 1 ) H ( z ) or the calibrated simulation, one of the fine DA elements was adjusted to correct the gain ratio between the coarse and fine DAs. The simulation results for the calibrated system and the power spectrum density of its output signal are shown in figures 9 and 10 respectively. or the mismatch of 1% the results show that the calibrated system has a drop of only 0.5 db in the SNR which is much lower than that of the segmented system. (11) (.Q ( z ))(1 z 1 ) 2 H ( z ) 1 (1 )(1 z 1 ) H ( z ) which shows that that the coarse quantization noise leakage is first-order shaped. Simulations show that higher order REQ is not necessary, first order REQ sufficiently suppresses coarse/ fine mismatch errors below the noise shaped by the DWA within each DA. 6. Simulation Results In order to verify the validity of the proposed calibration and REQ methods in this paper a second order sigma delta modulator with 8-bit quantizer (4 bit coarse, 4 bit fine) and an OSR of 30 has been simulated using MATLAB. igure 8 shows the simulation results for both segmented and single-path systems versus various unit-element mismatch percentages. The element sizes were selected assuming that the coarse element percent mismatch be (24)1/2 times lower than the fine element mismatch due to the 24 sizing ratio. As shown in figure 8, with the addition of unit element mismatch, the overall SNR of the segmented system drops much faster than the single-path system. The results of simulation show the SNR of segmented system with 1% mismatch, is 20 db lower than that of single-path system. igure 8. Simulated results for segmented system igure 9. Simulated results for calibration system 37 SSDR@SIENEREORD.OM

7 igure 10. Power spectrum density of output the Σ modulator using calibration method igure 11. Simulated Results for REQ system igure 11 compares the performance of the segmentation and ReQ methods against the single-path method. Again, a (4+4) bit quantizer, second-order modulator with an OSR of 30 was used, and also the coarse and fine percent mismatches were scaled assuming a 16:1 size ratio between coarse and fine elements. The figure 12 shows power spectrum density of the output signal for REQ system for the case of 1% fine element mismatch. The ReQ method achieves an average SNR of db, which is only 2 db less than that of the full 8-bit DWA method however number of unit elements of DWA circuit much less than that of single-path method. The simulated results are summarized in Table 1. igure 12. Power spectrum density of output the Σ modulator using requantization method Table1: Simulated Results 38 SSDR@SIENEREORD.OM

8 7. onclusion The DWA algorithm modulates the nonlinarity error of the DA due to mismatch unit elements, moving the harmonic distortion out of the signal bandwidth. However each added bit of quantizer casuses an exponential increase in complexity of DWA and DA circuitry. The segmented architecture with coarse/fine DA and DWA combined with either the calibration or ReQ methods proposed in this paper allow for larger internal quantizers without the exponential increase in DWA logic, while still maintaining performance close to the single path system. References [1] S. R. Norsworthy, R. Schreier, and G.. Temes, Delta-Sigma Data onverters, IEEE Press, [2] R. Schreier and G.. Temes, Understanding Delta-Sigma Data onverters,hoboken, NJ: Wiley, [3] R. Jiang and T. S. iez, A 1.8V 14b Delta-Sigma A/D onverter with 4Msamples/s onversion, Digest of Technical Papers, IEEE 2002 International Solid-State ircuits onference (ISS), vol. 1, pp , eb doi: /iss [4] R. Koch, B. Heise,. Eckbauer, E. Engelhardt, J. A. isher, and.parzefall, A 12-bit sigma-delta analog-to-digital converter with a 15-MHz clock rate, IEEE Journal of Solid-State ircuits, vol. 21, pp , Dec doi: /jss [5] M. Rebeschini, N. R. van Bavel, P. Rakers, R. Greene, J. aldwell, and J. R. Haug, A 16-b 160-kHz MOS A/D converter using sigma-delta modulation, IEEE Trans. ircuits Syst, vol. 25, pp , Apr doi: / [6] S. Lindfors and K. A. I. Halonen, Two-step Quantization in Multibit Delta-Sigma Modulators, IEEE Transactions on. ircuits and systems II, vol. 48, no. 2, pp , eb doi: / [7] Y. heng,. Petrie and B. Nordick, A 4th-Order Single- Loop Delta-Sigma AD with 8-Bit Two-Step lash Quantization, submitted to Proc. ISAS 2004,pp , Oct doi: /isas [8] R. T. Baud and T. S. iez, Linearity Enhancement of Multibit AID and D/A onverters Using Data Weighted Averaging, IEEE Transactions on ircuits and Systems II. 119 vol. 42, pp , Dec doi: / [9] R. Adams, K. Nguyen, and K. Sweetland, A 113-dB SNR Oversampling DA with Segmented Noise-Shaped Scrambling, IEEE Journal of Solid-State ircuits, pp , Dec doi: / [10] Brent Nordic, raig Petrie, and Yongjie heng, Dynamic Element Matching Techniques or Delta-Sigma ADS With Large Internal Quantizers Accepted to Proc IEEE International Symposium on ircuits and Systems (ISAS), vol. 1,pp , May doi: /isas [11] I. Galton, Why Dynamic-Element-Matching DAs Work, IEEE Transactions on ircuits and Systems II: Express Briefs, vol. 57, no. 2, pp ,ebruary2010. doi: /tsii [12] A. A. Hamoui and K. W. Martin, High-order multibit modulators and pseudo data weighted-averaging in low-oversampling AS ADs for broad-band applications, IEEE Transactions on ircuits and Systems I, vol. 51, pp , Jan doi: /tsi [13] E. Najafi Aghdam, P. Benabes,J. Abbasszadeh ompletely first order and tone free partitioned data weighted averaging technique used in a multibit delta sigma modulator, IEEE 19th European onference on ircuit Theory and Design (EDT'09), Antalya, pp , doi: /etd [14] A. Lavzin, M. Kozak,G. riedman A Higher-Order Mismatch-Shaping Method for Multi-Bit Sigma-Delta Modulators, In Proceedings of So, pp , doi: /so [15] S. Zouari, H. Daoud, M. Loulou, P. Loumeau, N. Masmoudi, High Order ascade Multibit ΣΔ Modulator for Wide Bandwidth Applications, International Journal of Electrical and omputer Engineering, SSDR@SIENEREORD.OM

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