A Novel Fully-Differential Second-Generation Current- Conveyor Based Switched-Capacitor Resonator

Transcription

1 2012, TextRoad Publication ISSN Journal of Basic and Applied Scientific Research A Novel Fully-Differential Second-Generation Current- Conveyor Based Switched-Capacitor Resonator Mostafa Moridi (1) and Hooman Kaabi (2) (1) Department of Electronic Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran (2) Department of Electrical Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran ABSTRACT In this paper a novel structure for Direct Charge Transfer Pseudo-N-Path (DCT-PNP) resonator based on Fully Differential Second Generation Current Conveyor (FDCCII), is presented. This structure not only had the advantages of the conventional opamp based DCT-PNP, but also the capability of switching at high frequencies due to the inherent characteristics of CCII. Furthermore, the number of the switches was reduced to 21 compared with the traditional DCT-PNP resonator which had 24 switches. The proposed resonator was simulated by means of HSPICE and WAVEVIEW in 0.35µm CMOS technology. KEY WORDS: Resonator, SC Circuit, SC Filter, Band Pass Sigma-Delta Modulator (BPSDM), CCII 1. INTRODUCTION Sigma-Delta modulation has become a widely applied technique for high-performance analog-to-digital (A/D) conversion of narrow-band signals [1, 2]. Direct digitization of signals in wireless communications needs band-pass Sigma-Delta modulators [3, 4]. These are used to digitize the received analog signal at an intermediate center frequency [3, 4]. These modulators are usually implemented using high speed switched capacitor resonators, which are tuned to a particular frequency [5, 6, 7]. A resonator must be designed such that it has a sharp resonant peak at a specific center frequency. There exist many resonator circuits to implement SC band pass Sigma-Delta modulators and filters for high-frequency applications, such as: the Lossless-Discrete Integrator (LDI) [8], Two- Delay Loop (TDL) [9], Pseudo-Two-Path (P2P) [10], Integrating two Path (I2P) [11] and finally Direct Charge Transfer Pseudo-N-Path (DCT-PNP) [12]. Compared with the mentioned structures, DCT-PNP is the most insensitive structure to opamp non idealities [12]. Due to the inherent high frequency capability of CCII building block [13], it is an attractive candidate for replacing opamps in the traditional resonator circuits. Some efforts have been done earlier to design resonators based on CCII [14, 15]. The new structure is a CCII version of DCT-PNP resonator. Thus inherits all of DCT-PNP advantages plus the higher frequency operation due to utilizing CCII building block. 2. PROPOSED RESONATOR The ideal transfer function of the proposed resonator is given by: H(Z) = (1) This translates into the input-output relation; V out (n+2) = -V out (n) + V in (n). Fig. 1 shows the proposed resonator [16]. As the traditional DCT-PNP, a Fully differential structure is selected to implement resonator. In order to implement fully differential structure, FDCCII is used. The relation between its terminal signals is given by [16]: I I V V V = I V I I 0 0 ± V I ±1 0 0 V (2) *Corresponding Author: Mostafa Moridi Department of Electronic Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran, M.Moridi@qiau.ac.ir 8235

2 Moridi and Kaabi, 2012 The (+) and (-) factors in (2), describe FDCCII+ and FDCCII-, respectively. Fig. 1 The proposed resonator followed by clock pulse scheme [16] Some structures for the FDCCII have been proposed in the literature [17, 18, 19]. The FDCCII-, which is used here, is shown in Fig. 2. Time sharing of the voltage and current buffers of FDCCII-, is used to produce the inputoutput relation of the resonator. Fig. 3 shows the resonator at the phase c. As traditional resonator, during the phase c, C 1p and C 1n hold the differential output voltage V out (n) (Note that: V y1 = V x1 and V y2 = V x2 ). At this phase, C 3p and C 3n, are connected between the input and the output of the resonator therefore, they are charged to V out (n)+v in (n) and V out (n)-v in (n), respectively. After two clock phases (2T), the C 3 capacitors will be connected to Y terminals, thus providing V out (n+2). Because Ix 1 = -Iz 1 and Ix 2 = -Iz 2, two current loops are made to prevent the connection of the Z terminals to the virtual ground. Furthermore, connecting the bottoms of the C 1 capacitors, in the phase c, forces them to have no path to the virtual ground. Therefore, like traditional DCT-PNP resonator, there is no charge transfer path to the virtual ground. Fig. 2 Schematic of Fully-Differential Second-Generation Current-Conveyor (FDCCII-) [16] 8236

3 Fig. 3 The proposed resonator at the phase c [16] Since the same capacitor samples the input and subtracts it from the previous output, to provide the delayed output, the proposed resonator did not affected by the capacitor mismatches. Taking into account the gain error, the actual transfer function is given by: H(Z) = ( ) (3) where the error term d depends on both, the current gain of the current copier and the voltage gain of the voltage buffer. As it is shown in Fig. 1, another advantage of the proposed resonator is that the number of switches is reduced to 21. In traditional DCT-PNP resonator the number of switches was 24. In switched-capacitor BPSDMs, the analogue and digital parts are implemented on the same board. In these circuits, one of the main sources of noise is the switching noise (thermal and on resistance noise of the switches), compared to the quantization noise of quantizer. Therefore, the reduction of the number of switches reduces the switching noise of the circuit. For more discussion regarding the switching noise one can refer to [20]. 3. SIMULATION RESULTS Simulation of proposed resonator did by means of HSPICE and WAVEVIEW. The circuit which used to simulate the FDCCII-, is shown in Fig. 4. Transistor aspect ratios are listed in Table. 1. Current conveyor was designed based on [21] in 0.35µm CMOS technology. Fig. 4 The circuit of FDCCII- [16] 8237

4 Moridi and Kaabi, 2012 Transistor name M7 M10 M18 M21 M9 M11 M20 M22 M5 M16 M1 M2 M12 M13 M3 M4 M14 M15 M6 M17 M8 M22 Transistor Aspect Ratio (W/L) (µm / µm) / / / / / / / 0.35 Table. 1 Transistor aspect ratios for the circuit shown in Fig. 4 The resonator simulated at 10 MHz sampling frequency. Furthermore, the amplitude and the frequency of the input signal were considered to be 1V and 2.5 MHz, respectively. FFT simulation was taken by WAVEVIEW with 2048 points. Here, the capacitors were set to be C 1p = C 2p = C 3p = C 1n = C 2n = C 3n = 0.1pF. The switches were modeled by voltage controlled resistors. The result of the FFT simulation is shown in Fig. 5. Fig. 5 FFT simulation of the proposed resonator [16] 4. CONCLUSION A new resonator was proposed. Compared with traditional DCT-PNP, 3 switches were eliminated. This structure not only had the advantages of the conventional opamp based DCT-PNP, but also the capability of switching at high frequency due to the inherent characteristics of CCII. REFERENCES [1] Candy, J. C. and G. C. Temes, Oversampling methods for A/D and D/A conversion. In: Oversampling Delta Sigma Data Converters (eds. J.C. Candy and G. C. Temes). IEEE Press, New York. [2] Norsworthy, S. R., R. Schreier and G. C. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation. IEEE Press, New York. [3] Schreier, R. and M. Snelgrove, Nov Bandpass sigma-delta modulation. Electron. Lett., 25:

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