EE247 Lecture 11. Switched-Capacitor Filters (continued) Effect of non-idealities Bilinear switched-capacitor filters Filter design summary

Transcription

1 EE47 Lecture 11 Switched-Capacitor Filters (continued) Effect of non-idealities Bilinear switched-capacitor filters Filter design summary Comparison of various filter topologies Data Converters EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 1 Summary Last Lecture Switched-capacitor filter design considerations DDI & LDI Integrator characteristics Bottom-plate LDI integrator overcomes parasitic sensitivity issues Continuous-time and complex conjugate terminations Use of T-networks to implement high capacitor ratios Switched-capacitor filters utilizing double sampling technique Effect of non-idealities Opamp finite gain Opamp finite bandwidth Finite slew rate of the opamp (this lecture) EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page

2 Switched-Capacitor Direct-Transform Discrete (DDI) Integrator Vin C φ I 1 φ - φ 1 φ 1 φ T=1/f s V o V in (z) = Cs z z Cs 1 z 1 = EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 3 DDI Switched-Capacitor Integrator Vin φ 1 φ - φ 1 Cs z 1 jωt (z) =, z= e 1 V 1 z in Cs s j T / j j 1 C e ω α α = = since: sinα = e e jωt jωt / jωt / 1 e e e j Cs jωt / = j e 1 sin( ωt/) Cs 1 ωt/ jωt / = e jω T sin( ωt/) Phase Error Ideal Integrator Magnitude Error EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 4

3 DDI Switched-Capacitor Integrator Example: Mag. & phase error for: 1- f max sig./ f s = 1/1 Mag. error = 1% or 0.1dB Phase error=-ωt/= -π f / f s = -π /1 [radian] 15 [degree] Q intg 1/( phase ο in radian ) (Lecture 5 page 1) Q intg = -1/π = f / f s =1/3 Mag. error=0.16% or 0.014dB Phase error = ω T/= -π f / f s = -π /3 [radian] 5.6 [degree] Q intg = -3/π = -10. DDI Integrator: Magnitude error no problem Phase error major problem EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 5 Vin φ 1 φ - φ 1 LDI Switched-Capacitor Integrator LDI (Lossless Discrete Integrator) same as DDI but output is sampled ½ Vin clock cycle earlier LDI V o Cs z 1/ jωt (z) =, z= e 1 V 1 z in Cs e jωt / C = = s 1 jωt jωt/ jωt/ 1 e e e C = j s 1 sin( ωt/) φ 1 φ - φ C = s 1 jω T Ideal Integrator ωt/ sin( ωt/) Magnitude Error No Phase Error! For signals at frequencies << sampling freq. Magnitude error negligible EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 6

4 Switched-Capacitor Integrator Parasitic Sensitivity Vin p φ 1 φ C p3 C - C p1 Effect of parasitic capacitors: 1- C p1 - driven by opamp o.k. - C p - at opamp virtual gnd o.k. 3- C p3 Charges to Vin & discharges into Problem parasitic sensitivity EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 7 Parasitic Insensitive Bottom-Plate Switched-Capacitor Integrator Sensitive parasitic cap. C p1 rearrange circuit so that C p1 does not charge/discharge φ1=1 C p1 grounded φ=1 C p1 at virtual ground C p driven by a low impedance source φ 1 φ s C p1 C - Vi C p Vi- Solution: Bottom plate capacitor integrator EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 8

5 Bottom Plate Switched-Capacitor Integrator Vi φ1 φ - Note: Different delay from Vi & Vi- to either output Special attention needed for input/output connections φ 1 φ Vi on φ1 Vi- Vion φ 1 Output/Input z-transform 1 on φ1 on φ Cs 1 z Cs 1 z 1 1 z 1 1 z 1 Cs C z s z 1 z EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 9 Bottom Plate Switched-Capacitor Integrator z-transform Model Vi C φ1 φ I 1 1 z -z z 1 z 1 z 1 Input/Output 1 z-transform 1 1 z 1 z Viφ 1 φ 1 Vi Vi- Cs Cs z z 1 z 1 z 1 LDI EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 10

6 LDI Switched-Capacitor Ladder Filter sτ 3 sτ 4 sτ z 1 C C z s I 1 1 z 1 z 1 1 z z z 1 z 1 1 z 1 z 1 z C s z C s Delay around integrator loop is (z -1/. z 1/ =1) LDI function EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 11 Effect of Opamp Nonidealities on Switched Capacitor Filter Behaviour Opamp finite gain Opamp finite bandwidth Finite slew rate of the opamp Non-linearities associated with opamp output/input characteristics EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 1

7 Effect of Opamp Non-Idealities Finite DC Gain φ1 φ Cs 1 H(s) fs C s f s 1 s C I a ωo H(s) s ω 1 o a Vi - DC Gain = a Input/Output z-transform Q a Finite DC gain same effect in S.C. filters as for C.T. filters If DC gain not high enough causes lowing of overall Q & droop in passband EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 13 Vi Vi- Vi- φ1 φ Effect of Opamp Non-Idealities Finite Opamp Bandwidth - Unity-gain-freq. Input/Output z-transform = f t V o φ settling error T=1/f s time Assumption- Opamp does not slew (will be revisited) Opamp has only one pole exponential settling Ref: K.Martin, A. Sedra, Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched- Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-8, no. 8, pp. 8-89, Aug EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 14

8 Vi Vi- φ1 φ Effect of Opamp Non-Idealities Finite Opamp Bandwidth - Unity-gain-freq. Input/Output z-transform = f t V o φ settling error T=1/f s time k k 1 H actual (Z) H 1 e e Z ideal(z) Cs where k = π ft Cs fs ft Opamp unity gain frequency, fs Clock frequency Ref: K.Martin, A. Sedra, Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched- Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-8, no. 8, pp. 8-89, Aug EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 15 - f c /f s =1/3 f c /f t ~0.0 f t >45f c Effect of Opamp Finite Bandwidth on Filter Magnitude Response Τ non-ideal / Τ ideal (db) Example: For 1dB magnitude response deviation: 1- f c /f s =1/1 Active RC f c /f t ~0.04 f t >5f c f c /f s =1/3 f c /f s =1/1 3- Cont.-Time f c /f t ~1/700 f t >700f c fc /f t EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 16

9 Effect of Opamp Finite Bandwidth on Filter Critical Frequency Example: For maximum critical frequency shift of <1% 1- f c /f s =1/3 f c /f t ~0.08 f t >36f c - f c /f s =1/1 f c /f t ~0.046 f t >f c Δω c /ω c Active RC f c /f s =1/3 f c /f s =1/1 3- Active RC f c /f t ~0.008 f t >15f c C.T. filters f c /f t Ref: K.Martin, A. Sedra, Effect of the Opamp Finite Gain & Bandwidth on the Performance of SwitchedCapacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-8, no. 8, pp. 8-89, Aug EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 17 Opamp Bandwidth Requirements for Switched- Capacitor Filters Compared to Continuous-Time Filters Finite opamp bandwidth causes phase lag at the unity-gain frequency of the integrator for both type filters Results in negative intg. Q & thus increases overall Q and results in peaking in the passband of interest For given filter requirements, opamp bandwidth requirements much less stringent for S.C. filters compared to cont. time filters lower power dissipation for S.C. filters (at low freq.s only) Finite opamp bandwidth causes down shifting of critical frequencies in both type filters Since cont. time filters are usually tuned tuning accounts for frequency deviation S.C. filters are untuned and thus frequency shift could cause problems specially for narrow-band filters EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 18

10 Sources of Distortion in Switched- Capacitor Filters Distortion induced by finite slew rate of the opamp Opamp output/input transfer function nonlinearity- similar to cont. time filters Distortion incurred by finite setting time of the opamp Capacitor non-linearity- similar to cont. time filters Distortion due to switch clock feed-through and charge injection EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 19 What is Slewing? Vin φ - C L V o Viφ Vi Assumption: Integrator opamp is a simple class A transconductance type differential pair with fixed tail current Iss Iss EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 0

11 What is Slewing? Opamp I o v.s. V in I o I max= I ss/ Slope ~ g m V o I o V max V in φ I max= -I ss/ Vi- V Cs > V max Output current constant I o =Iss/ or Iss/ V o ramps down/up Slewing After Vcs is discharged enough to have: V Cs <V max I o =gm V Cs Exponential or over-shoot settling Iss Vi EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 1 Distortion Induced by Opamp Finite Slew Rate Output ltage Multiple pole settling One pole settling Slewing Settling Settling (multi-pole) Time EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page

12 Ideal Switched-Capacitor Output Waveform Vin φ 1 - Clock φ 1 φ Vin Vin φ - Vcs φ High Charge transferred from Cs to EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 3 Slew Limited Switched-Capacitor Integrator Output Slewing & Settling Clock φ 1 φ -ideal -real Slewing Linear Settling Slewing Linear Settling EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 4

13 Distortion Induced by Finite Slew Rate of the Opamp Ref: K.L. Lee, Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb (ERL Memorandum No. UCB/ERL M86/1). EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 5 Distortion Induced by Opamp Finite Slew Rate Error due to exponential settling changes linearly with signal amplitude Error due to slew-limited settling changes non-linearly with signal amplitude (doubling signal amplitude X4 error) For high-linearity need to have either high slew rate or non-slewing opamp ω ( os ) T V 8 o sin HD k = ST r s π k ( k 4 ) 8( sin ωos T ) 8π f HD o 3 = for fo >> fs HD ST 3 r s 15π 15Sr fs Ref: K.L. Lee, Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb (ERL Memorandum No. UCB/ERL M86/1). EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 6

14 Example: Slew Related Harmonic Distortion ω ( os ) T V 8 o sin HD 3 = ST r s 15π 8π f HD o 3 15S r f s 1dB Switched-capacitor filter with 4kHz bandwidth, f s =18kHz, S r =1V/μsec, V o =3V Ref: K.L. Lee, Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb (ERL Memorandum No. UCB/ERL M86/1). EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 7 Distortion Induced by Opamp Finite Slew Rate Example HD3 [db] V o =1V f / f s =1/3 V o =V f / f s =1/1 V o =1V V o =V (Slew-rate / f s ) [V] EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 8

15 Distortion Induced by Finite Slew Rate of the Opamp Note that for a high order switched capacitor filter only the last stage slewing will affect the output linearity (as long as the previous stages settle to the required accuracy) Can reduce slew limited linearity by using an amplifier with a higher slew rate only for the last stage Can reduce slew limited linearity by using class A/B amplifiers Even though the output/input characteristics is non-linear as long as the DC open-loop gain is high, the significantly higher slew rate compared to class A amplifiers helps improve slew rate induced distortion In cases where the output is sampled by another sampled data circuit (e.g. an ADC or a S/H) no issue with the slewing of the output as long as the output settles to the required accuracy & is sampled at the right time EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 9 More Realistic Switched-Capacitor Circuit Slew Scenario Vin φ - C L φ t=0 C L At the instant connects to input of opamp (t=0) Opamp not yet active at t=0 due to finite opamp bandwidth delay Feedforward path from input to output generates a voltage spike at the output with polarity opposite to final step- spike magnitude function of, C L, Spike increases slewing period Eventually, opamp becomes active - starts slewing followed by subsequent settling EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 30

16 Switched-Capacitor Circuit Opamp not t=0 Vin φ φ - C C L s t=0 ( ) t0 t0 I L s Cs = Cs s eq eq = CL Charg e sharing : C V V C C where C C C C Δ V = V = V t0 t0 I t0 s I out Cs Cs CL Cs Ceq CL CC ( ) t0 t0 t0 t0 L << s<< I eq L s Cs Cs s L Cs Cs AssumingC C C C C CV V C C V V C C ΔV V V t0 t0 s I t0 out Cs Cs Cs CL CL Cs Cs Note that ΔV V V C C final t0 t0 out Cs Cs I I C L EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 31 More Realistic Switched-Capacitor Circuit Slew Scenario Vin φ φ - C C L s t=0 C L Notice that if C L is large some of the charge stored on Cs is lost prior to opamp becoming effective operation looses accuracy CC Charg e sharing : C V V C C where C C V V V t0 t0 s t0 Cs = Cs = Cs Cs Ceq ( ) t0 t0 I L s Cs = Cs s eq eq = CL Cs C L Cs C C I L Partly responsible for S.C. filters only good for low-frequency applications EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 3

17 More Realistic S.C. Slew Scenario _ideal _real _real Including t=0 spike Slewing Linear Settling Slewing Linear Settling Spike generated at t=0 Slewing Linear Settling Slewing Ref: R. Castello, Low ltage, Low Power Switched-Capacitor Signal Processing Techniques," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Aug. 84 (ERL Memorandum No. UCB/ERL M84/67). EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 33 Sources of Noise in Switched- Capacitor Filters Opamp Noise Thermal noise 1/f (flicker) noise Thermal noise associated with the switching process (kt/c) Same as continuous-time filters Precaution regarding aliasing of noise required EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 34

18 Bilinear integrator Other z domain Integrators Example: Bilinear ( ) = ( ) ( ) ( ) vo nt vo nt T k vi nt vi nt T z ( z) k 1 z = Vi( z) ( z) 1 z H( z) = = k V ( z) 1 z i 1 1 EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 35 Bilinear Integrator - Not implemented by standard SC integrators - Synthesis: Biquads: direct coefficient comparison Example: Bilinear S.C. integrator: Cs 1 Z 1 1 H(Z ) = 1 Z Cs 1e jωt jωt 1 e Cs 1 ωts jωts tan ωts = = Ideal Integrator Magnitude Error No Phase Error! For signals at frequency <<sampling freq. Magnitude error negligible Ref: R. Gregorian, G. Temes, Analog CMOS Integrated Circuits," Wiley, 1986, pp 77. EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 36

19 LDI : Bilinear LDI & Bilinear Transformation Frequency Warping 1 Z 1/ T = s 1 1 s 1 Z jsin ωts s jsin ωts Ts 1 1 Z 1 1e j ωt T = s 1 1 j T s 1 Z 1 e = ω jtan ωts s jtan ωts Ts EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 37 Other z domain Integrators Example: Bilinear Frequency translation 1 s s= π jf RC = HSC ( z) z= e π jfsct fs f tan SC frc = π π fs Bilinear f RC f s f = π π sin f SC s LDI EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 38

20 Bilinear Transform f sc /f s f RC /f s f RC f s f = π π tan f SC Entire jω axis maps onto the unit circle Mapping is nonlinear (tan distortion) prewarp specifications of RC prototype Matlab filter design automates this (see, e.g. bilinear) s EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 39 Bilinear & LDI Transformation Frequency Warping As long as f<<f s error negligible EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 40

21 Bilinear Bandpass f s = 100kHz f c = f s /8 Q = 10 zero at f s / Pole-Zero Map Imag Axis 0-0. Matlab: z^ H(z) = z^ z Real Axis EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 41 Martin-Sedra Biquad K4 CA = 1.15pF phi1 phi1 Periodic AC Analysis PAC1 log sweep from 1k to 50k (300 steps) phi phi CLK1 fs = 100kHz K6 CA = 151.fF CA = 1pF CB = 1pF Vi K1 CA = 0F phi1 phi1-1m K5 CB = 500fF phi1 phi -1M phi phi phi phi1 V1 ac = 1V K CA = 151.fF K3 CB = 37.8fF V () z () z i K3z = z ( K3 K1K5 KK5) z ( K3 KK5) ( K K K K ) z ( 1 K K ) Ref: K. Martin and A. S. Sedra, Strays-insensitive switchedcapacitor filters based on the bilinear z transform, Electron. Lett., vol. 19, pp , June EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 4

22 Magnitude Response Magnitude [db] Frequency [Hz] x 10 5 EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 43 LDI vs Bilinear Transform LDI transform: Realized by standard switched-capacitor integrators Some high frequency zeros may get lost Simple filter synthesis: Replace RC integrators with SC integrators Ensure clock phases chosen so that all integrators loops LDI type Bilinear transform Not implemented by standard SC integrators Synthesis: Biquads: direct coefficient comparison Ladders: see R. B. Datar and A. S. Sedra, Exact design of strays-insensitive switched capacitor high-pass ladder filters, Electron. Lett., vol. 19, no 9, pp , Nov EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 44

23 Switched-Capacitor Filter Application Example: ice-band Codec (Coder-Decoder) Chip f s = 104kHz f s = 18kHz f s = 8kHz f s = 8kHz f s = 18kHz f s = 8kHz f s = 18kHz f s = 18kHz Ref: D. Senderowicz et. al, A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip, IEEE Journal of Solid-State Circuits, l.-sc-17, No. 6, pp , Dec EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 45 CODEC Transmit Path Lowpass Filter Frequency Response 0 Note: f s =18kHz Magnitude (db) Frequency (Hz) EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 46

24 CODEC Transmit Path Highpass Filter 0 Magnitude (db) Frequency (Hz) Note: f s =8kHz EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 47 CODEC Transmit Path Filter Overall Frequency Response 0 Magnitude (db) Frequency (Hz) Low Q bandpass (Q<1) filter shape Implemented with lowpass followed by highpass EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 48

25 CODEC Transmit Path Clocking Scheme First filter (1 st order RC type) performs anti-aliasing for the next S.C. biquad The first stage filters form 3 rd order elliptic with corner 3kHz Anti-aliasing for the next lowpass filter The stages prior to the high-pass perform anti-aliasing for highpass Notice gradual lowering of clock frequency Ease of anti-aliasing EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 49 SC Filter Summary Pole and zero frequencies proportional to Sampling frequency f s Capacitor ratios High accuracy and stability in response Long time constants realizable without large R, C Compatible with transconductance amplifiers Reduced circuit complexity, power dissipation Amplifier bandwidth requirements less stringent compared to CT filters (low frequencies only) Issue: Sampled-data filters require anti-aliasing prefiltering EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 50

26 Switched-Capacitor Filters versus Continuous- Time Filter Limitations Considering overall effects: Opamp finite unitygain-bandwidth Opamp settling issues Opamp finite slew rate Clock feedthru Switch sampling cap. finite timeconstant Magnitude Error 5-10MHz Cont. Time Filter S.C. Filter Filter bandwidth Assuming constant opamp f u Limited switched-capacitor filter performance frequency range EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 51 Summary Filter Performance versus Filter Topology Opamp-RC Max. Usable Bandwidth ~10MHz SNDR 60-90dB Freq. tolerance w/o tuning % Freq. tolerance tuning 1-5% Opamp- MOSFET-C ~ 5MHz 40-60dB % 1-5% Opamp- MOSFET-RC ~ 5MHz 50-90dB % 1-5% Gm-C ~ 100MHz 40-70dB % 1-5% Switched Capacitor ~ 10MHz 40-90dB <<1% _ EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 5

27 Data Converters EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 53 Material Covered in EE47 Where are We? Filters Continuous-time filters Biquads & ladder type filters Opamp-RC, Opamp-MOSFET-C, gm-c filters Automatic frequency tuning Switched capacitor (SC) filters Data Converters D/A converter architectures A/D converter Nyquist rate ADC- Flash, Pipeline ADCs,. Oversampled converters Self-calibration techniques Systems utilizing analog/digital interfaces EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 54

28 Data Converter Topics Basic operation of data converters Uniform sampling and reconstruction Uniform amplitude quantization Characterization and testing Common ADC/DAC architectures Selected topics in converter design Practical implementations Desensitization to analog circuit non-idealities Figures of merit and performance trends EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 55 Suggested Reference Texts R. v. d. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, nd ed., Kluwer, 003. B. Razavi, Data Conversion System Design, IEEE Press, S. Norsworthy et al (eds), Delta-Sigma Data Converters, IEEE Press, Extensive treatment of oversampled converters including stability, tones, bandpass converters. J. G. Proakis, D. G. Manolakis, Digital Signal Processing, Prentice Hall, EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 56

29 Converter Applications EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 57 Data Converter Basics DSPs benefited from device scaling However, real world signals are still analog: Continuous time Continuous amplitude DSP can only process: Discrete time Discrete amplitude Need for data conversion from analog to digital and digital to analog Analog Input Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Postprocessing Analog Output Filters? ? Filters EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 58

30 A/D & D/A Conversion A/D Conversion D/A Conversion EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 59 Data Converters Stand alone data converters Used in variety of systems Example: Analog Devices AD935 1bit/ 65Ms/s ADC- Applications: Ultrasound equipment IF sampling in wireless receivers Various hand-held measurement equipment Low cost digital oscilloscopes EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 60

31 Data Converters Embedded data converters Cost, reliability, and performance Integration of data conversion interfaces along with DSPs Main issues Feasibility of integrating sensitive analog functions in a technology optimized for digital performance Down scaling of supply voltage Interference & spurious signal pick-up from on-chip digital circuitry Portable applications dictate low power consumption EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 61 Example: Typical Cell Phone Contains in integrated form: 4 Rx filters 4 Tx filters 4 Rx ADCs 4 Tx DACs 3 Auxiliary ADCs 8 Auxiliary DACs Total: Filters 8 ADCs 7 DACs 1 Dual Standard, I/Q Audio, Tx/Rx power control, Battery charge control, display,... EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 6

32 D/A Converter Transfer Characteristics For an ideal digital-to-analog converter accepting digital inputs b 1 - b n and producing either an analog output voltage or current with: uniform, binary digital encoding & a unipolar output ranging from 0 to V FS Nomenclature: MSB LSB b 1 b b 3 b n.. D/A V 0 N = # of bits V FS = full scale output Δ= min. step size 1LSB VFS Δ= N VFS or N = log resolution Δ V = V N i= 1 N bi 0 FS i i= 1 N i =Δ bi, bi = 0 or 1 EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 63 D/A Converter Exampe: D/A with 3-bit Resolution Example:N = 3 Assume VFS = 0.8V Input code is ( ) V =Δ b b b Then: Δ= V / = 0.1V FS 3 ( 1 0) V0 0.1V = = V = 0.5V 0 MSB LSB b 1 b b D/A V 0 Note:MSB V / & LSB V / FS FS N EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 64

33 Ideal DAC introduces no error! Ideal D/A Transfer Characteristic V FS Analog Output Ideal Response One-to-one mapping from input to output V FS / Step Height (1LSB =Δ) V FS / Digital Input Code EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 65 A/D Converter Transfer Characteristic For an ideal analog-to-digital converter with uniform, binary digital encoding & a unipolar input range for 0 to V FS where m = # of bits MSB LSB b 1 b b 3 b m.. D/A V 0 VFS = full scale output Δ= step size V Δ= FS m Note:D ( b = 1,alli) VFS i Δ 1 1 VFS m EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 66

34 Ideal A/D Transfer Characteristic Ideal ADC introduces error (-1/ Δ) Δ = V FS / m Digital Output m= # of bits This error is called ``quantization error`` LSB 0 Δ Δ 3Δ 4Δ 5Δ 6Δ 7Δ Analog input EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 67 Data Converter Performance Metrics Data Converters are typically characterized by static, time-domain, & frequency domain performance metrics : Static Monotonicity Offset Gain error Differential nonlinearity (DNL) Integral nonlinearity (INL) Dynamic Delay, settling time Aperture uncertainty Distortion- harmonic content Signal-to-noise ratio (SNR), Signal-to-(noisedistortion) ratio (SNDR) Idle channel noise Dynamic range & spurious-free dynamic range (SFDR) EECS 47 Lecture 11: S.C. Filters/ Data Converters 006 H. K. Page 68