Wenjuan Guo, Student Member, IEEE, Tsedeniya Abraham, Steven Chiang, Chintan Trehan, Masahiro Yoshioka, and Nan Sun, Member, IEEE

Transcription

1 656 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 62, NO. 7, JULY 2015 An Area- and Power-Efficient I ref Compensation Technique for Voltage-Mode R 2R DACs Wenjuan Guo, Student Member, IEEE, Tsedeniya Abraham, Steven Chiang, Chintan Trehan, Masahiro Yoshioka, and Nan Sun, Member, IEEE Abstract Although segmented voltage-mode R 2R digitalto-analog converters (DACs) have been widely used for highprecision DACs in static applications, its code-dependent reference current induces a code-dependent IR drop through the reference and ground wires, imposing a limitation on the linearity performance. To alleviate this problem, this brief proposes a simple way to compute the reference current and compensate it via a low-resolution auxiliary DAC controlled by a computational block. A(4+12)-bit segmented voltage-mode R 2R DAC with the proposed technique is designed and simulated in a 0.6-μm CMOS process. The SPICE simulation shows a six-time reduction of the integral nonlinearity error from the code-dependent reference current, greatly relaxing the requirement on the reference and ground distribution paths design. Compared with the conventional way of adding high-quality reference and ground buffers on chip, the proposed technique is estimated to take up 1/3 area and consume 1/5 power. With the scaling of the technology, the proposed technique becomes more competent, for 60% area comes from the purely digital computational block. Furthermore, for multichannel R 2R DACs, the computational block can be shared among channels if time multiplexing is allowed. Index Terms Code-dependent, digital-to-analog converter (DAC), reference current, R 2R. I. INTRODUCTION HIGH-RESOLUTION digital-to-analog converters (DACs) are widely used in industrial process-control applications such as programmable logic controllers and temperature controllers. In these applications, DAC is part of a sensor/controller feedback system and used for controlling such objects as motors and cylinders based on the sensors inputs. Therefore, dynamic performances such as spurious-free dynamic range and signal-to-noise-and-distortion ratio are not required, but we need high resolution and fast settling time to control the objects accurately and fast [1], [2]. Additionally, small area, low power, and simple design are desirable as they reduce the production cost. Manuscript received October 22, 2014; revised December 16, 2014; accepted February 11, Date of publication February 24, 2015; date of current version June 25, 2015.This work was supported in part by the National Science Foundation under Grant ECCS This brief was recommended by Associate Editor E. Bonizzoni. W. Guo and N. Sun are with the Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX USA ( wjguo@utexas.edu; nansun@mail.utexas.edu). T. Abraham, S. Chiang, C. Trehan, and M. Yoshioka are with Texas Instruments, Dallas, TX USA ( tsedeniya@ti.com; schiang@ti.com; ctrehan@ti.com; yoshioka@ti.com). Color versions of one or more of the figures in this brief are available online at Digital Object Identifier /TCSII With small device count and high resolution, the R 2R DAC is well suited for these applications [1], [2]. It is typically used in one of two operation modes. The current mode exploits the current division along the R 2R ladder, whereas the voltage mode is based on the voltage division. For a currentmode R 2R DAC, the major disadvantage is that it has a code-dependent output impedance, making it necessary to cascade an op-amp at the R 2R output. However, the codedependent output impedance still induces many problems in the op-amp, such as stability and dynamic offset [3]. In contrast, the voltage-mode R 2R has a constant output impedance, thereby avoiding all the aforementioned issues. Nevertheless, the voltage-mode R 2R DAC has a disadvantage that its reference impedance is code dependent. A code-dependent reference impedance induces a code-dependent current from the reference to the ground. To keep low cost and provide more flexibility to customers, the reference and ground tend to be provided off chip. Considering the wire resistances before the external reference and ground reach the R 2R ladder, there exists a code-dependent IR drop on the reference and ground lines, leading to linearity degradation. This degradation will become a main source of integral nonlinearity (INL) error as the target resolution increases. Even if there is an on-chip bandgap reference, for multichannel high-precision DACs, the reference and ground distribution path resistances still cannot be ignored. To alleviate the problem, the conventional way is to add a reference buffer and a ground buffer close to the R 2R ladder so that the wire resistances before the buffers will not affect the precision of the reference and ground. However, it is area, power, and time consuming to design two low-noise, small-offset, and small-output-impedance buffers [2], [4]. To avoid adding buffers, this brief proposes a simple background reference current compensation technique. The technique uses a low-resolution auxiliary DAC (AUXDAC) that shares the same reference and ground with the main R 2R DAC. The input to the AUXDAC comes from a computational block. Based on the input to the main R 2R DAC, it computes the current value we need to maintain a constant reference current. This way, we only get a fixed gain error rather than nonlinearity. The gain error can be easily removed by adjusting the reference value. Compared with buffers, the proposed technique is area and power efficient and has low design complexity. With the scaling of the technology, it will become more competent, for 60% area comes from the computational block, which is digital. In addition, for multichannel R 2R DACs, the computational block can be shared among channels if time multiplexing is allowed IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 GUO et al.: AREA- AND POWER-EFFICIENT I ref COMPENSATION TECHNIQUE FOR VOLTAGE-MODE R 2R DACs 657 Fig. 1. (log 2 (M +1)+N)-bit segmented voltage-mode R 2R DAC. Fig. 3. Equivalent model of a (log 2 (M +1)+N)-bit segmented voltagemode R 2R DAC. (a) When all MSB inputs are set to zero. (b) When all LSB inputs are set to zero. Fig. 2. Voltage-mode R 2R DAC equivalent model. Although [3] has already given a complete derivation of I ref, the extension from the binary model to the segmented model is quite complicated and indirect. To make it easier to derive and understand, we propose to divide I ref into three portions, i.e., I LSB induced by LSB, I MSB induced by MSB, and I INT induced by the interaction between LSB and MSB. By superposition, we have Although the nonlinearity error of an R 2R DAC can be also compensated via conventional calibration circuits [2] or predistortion blocks [5], they are based on measuring the output voltage error and, thus, need a prior knowledge about the reference and ground distribution path resistances, which cannot be properly controlled. Different from them, the proposed technique removes the nonlinearity error via compensating code-dependent reference current, which is independent of the path resistances. Furthermore, compared with [3], this brief proposes to divide the reference current in a segmented voltage-mode R 2R DAC into least significant bit (LSB), most significant bit (MSB), and interactive portions, which not only simplifies the reference current derivation but also makes the computational block design much easier. This brief is organized as follows. Section II proposes a simple way to derive the reference current in a segmented voltagemode R 2R DAC. Section III models the wire resistances on the reference and ground lines and demonstrates their effect on the linearity. Section IV proposes the reference current compensation technique and its circuit implementation for a (4+12)-bit segmented voltage-mode R 2R DAC. Section V shows the SPICE simulation results in a 0.6-μm CMOS process. Finally, Section VI concludes this brief. II. I ref DERIVATION In high-precision R 2R DACs, segmentation is commonly used to relax the resistor matching requirement and ensure the monotonic operation [6]. Fig. 1 shows the circuit diagram of a (log 2 (M +1)+N)-bit segmented voltage-mode R 2R DAC. The reference voltage is divided along the resistor network. The MSB 2R legs are controlled by the thermometercoded MSB inputs, i.e., t 1,t 2,...,t M, to connect to or the ground (Gnd), whereas the LSB 2R legs are controlled by the binary-coded LSB inputs, i.e., b 1,b 2,...,b M. An equivalent model of the voltage-mode R 2R DAC is shown in Fig. 2. As aforementioned, the output impedance R out is constant, whereas the reference impedance R ref is code dependent, leading to a code-dependent reference current I ref. I ref = I LSB + I MSB + I INT. (1) To get I LSB, we set all MSB inputs to zero, and thus, MSB is equivalent to a single resistor 2R/M connected to Gnd, as shown in Fig. 3(a). Similar to the derivation of the binary model in [3], we can derive I LSB as I LSB = 3R(M +1) + [ N N x 1 x=2 y=1 x=1 b x 2 M (M +1)2 2x+1 2 2x+1 b x b y 2 M +(M +1)2 2y 2 x+y which is the same as the binary model in [3] when M is zero. For I MSB, we set all LSB inputs to zero so that LSB is equivalent to a single resistor R connected to Gnd. Assuming that t 1,t 2,...,t k are high and t k+1,t k+2,...,t M are low, the R 2R DAC can be modeled as shown in Fig. 3(b). Therefore, we can easily derive I MSB as I MSB = k(m +1 k), 2R(M +1) k ] (2) M = t y. (3) y=1 If b x and t y are both high, there will be interactions between LSB and MSB. Through simple derivation, it can be found that the current injected into at t y due to b x and the current injected into at b x due to t y are equal, whose detailed expression is I INTx,y = I INTy,x = 2R(M +1) 2 x. (4) Therefore, the total I INT is I INT = R(M +1) N x=1 y=1 M b x t y 2 x. (5) Based on (1) (5), I ref in an ideal (4+12)-bit segmented voltage-mode R 2R DAC is computed, as shown in Fig. 4(a). Its compositions, i.e., I LSB, I MSB, and I INT, are further shown

3 658 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 62, NO. 7, JULY 2015 Fig. 6. INL and DNL results of an ideal (4+12)-bit segmented voltage-mode R 2R DAC with (a) R com =1Ωand (b) R com =10Ω( =2.5Vand R =40kΩ). Fig. 4. I ref in an ideal (4+12)-bit segmented voltage-mode R 2R DAC ( =2.5VandR =40kΩ). (a) I ref.(b)i LSB, I MSB,andI INT. Fig. 5. Modeling of the wire resistances on the and Gnd lines. (a) Singlechannel R 2R DAC. (b) Multichannel R 2R DACs. in Fig. 4(b). Here, ideal means ignoring the resistor mismatch and switch impedances. III. NONLINEARITY PROBLEM When the code-dependent I ref multiplies with the wire resistances on the and Gnd lines, a nonlinearity problem occurs at the DAC final output. Fig. 5 models the wire resistances on the and Gnd lines in the R 2R DAC. In the real implementation, a star connection is commonly adopted to connect each 2R leg to and Gnd. In a single-channel R 2R DAC, the star connection starts from the and Gnd pads, as shown in Fig. 5(a). Therefore, R com includes the bonding wire resistances and the printed circuit board metal trace resistances from the external reference/ground to the and Gnd pads. Here, we assume that and Gnd have the same R com to simplify the analysis, for it does not have any effect on the proposed technique. R sep are the metal trace resistances from the and Gnd pads to each 2R leg, which can be regarded as part of the mismatch of the 2R legs. For a high-resolution R 2R DAC, calibration is usually necessary to reduce the resistor mismatch. As long as the value of R is not too small, it is easy to make sure that R sep adds little burden to the existing calibration scheme. Therefore, our main problem falls on R com. For multichannel R 2R DACs sharing the same and Gnd pads, there are two-level R com,asshown in Fig. 5(b). The first-level R com1 is the same as the singlechannel R 2R DAC, and the second-level R com2 are the metal trace resistances from the and Gnd pads to each channel and Gnd pins. Both of them contribute to the codedependent IR drop of and Gnd, leading to a more serious nonlinearity problem. Note that, even if there is an on-chip bandgap reference, multichannel R 2R DACs still have the second-level R com2 from the bandgap reference to each channel R 2R DAC and Gnd pins. Since R com is much smaller than R, thevalueofi ref is determined by R. Therefore, when R is fixed, INL and differential nonlinearity (DNL) errors induced by the IR drop on the and Gnd lines are proportional to the value of R com. Fig. 6 shows the INL and DNL results of an ideal (4+12)- bit segmented voltage-mode R 2R DAC with R com =1Ω and R com =10Ω, respectively. As can be seen, even 1-Ω wire resistance already gives an error of 1.7 LSB INL and 0.4 LSB DNL. When R com increases to 10 Ω, INL and DNL become ten times worse. Therefore, it is necessary to develop an effective solution to address this issue. IV. PROPOSED REFERENCE CURRENT COMPENSATION TECHNIQUE Different from the conventional way of adding and Gnd buffers to reduce the effect of R com, a simple background reference current compensation technique is proposed, as shown in Fig. 7. We use an AUXDAC to share the same and Gnd with the main R 2R DAC. The AUXDAC is controlled by a computational block, which realizes a transfer function as I aux = I const I ref (6) where I const is the constant current through R com, and I aux is the output as digital codes to control the AUXDAC. To ensure I aux 0 and the smallest gain error, the best option for I const is the maximum value of I ref. As long as the current through R com is constant, we avoid the nonlinearity problem. This technique also applies to multichannel R 2R DACs. Although multichannel R 2R DACs have two-level R com,as shown in Fig. 5(b), if each channel R 2R DAC has a constant I ref, the current through R com of both levels will be code independent. Taking a (4+12)-bit segmented voltage-mode R 2R

4 GUO et al.: AREA- AND POWER-EFFICIENT I ref COMPENSATION TECHNIQUE FOR VOLTAGE-MODE R 2R DACs 659 Fig. 9. Comparison of the calculated I ref when the input bit number of the digital block is reduced from 16 to 15. Fig. 7. Proposed reference current compensation technique. TABLE I GATE COUNT OF THE COMPUTATIONAL BLOCK Fig. 8. Proposed architecture of the AUXDAC. DAC as an example, the detailed circuit implementations of the AUXDAC and the computational block are discussed in the following subsections. A. AUXDAC Fig. 8 shows the architecture of the AUXDAC. To avoid different process voltage temperature variations, the AUXDAC uses the same unit resistor as the main R 2R DAC. d i are the digital control signals from the computational block. As shown in Fig. 4(a), the (4+12)-bit segmented voltage-mode R 2R DAC has a I ref varying from 0 to 210 μa. To make the size of the AUXDAC reasonable, we use 16R in series for the last bit, giving an LSB step of 4 μa. With this LSB step, a 6-bit AUXDAC is enough to cover the range of 210 μa. Since 6 bit is much more relaxed than the resistor mismatch requirement for the main 16-bit R 2R DAC, the mismatch between the AUXDAC and the main R 2R DAC can be ignored. B. Computational Block To implement the computational block, it is important to decide the bit numbers of its input and output. The output bit number is decided by the resolution of the AUXDAC, which is 6 bit. As derived in Section II, I ref contribution is not subject to the rule of scaling down by 2 from MSB to LSB. Throwing away any bit causes a big error in estimating I ref.fig.9shows the comparison of the calculated I ref when the input bit number is reduced from 16 to 15. As can be seen, the estimation error of I ref reaches 21 μa after 1-bit reduction. As a result, the input bit number must be 16. Then, the straightforward implementation of the computational block is to build a mapping table from the 16-bit input to the 6-bit output based on (6) and apply the Quine McCluskey (QM) simplification method [7]. However, the QM method tries to explore all the input combinations to find a minimized Boolean function, giving a result whose complexity exponentially increases with the input bit number. After synthesis, the gate count of the digital block is , which is too huge to integrate it with the R 2R DAC. Since the QM method is not effective for a 16-bit input, the alternative way is to implement the I ref model. Compared with the model in [3], the proposed model, including (1) (5), not only simplifies the derivation but also makes the computational block design much easier. With I LSB, I MSB, and I INT implemented separately, the gate count of the computational block is reduced to 656 gates, which is a 194-time reduction from directly applying the QM method on the 16-bit input. The synthesis results are summarized in Table I. V. S IMULATION RESULTS With the proposed technique, a (4+12)-bit segmented voltage-mode R 2R DAC is designed and simulated in a 0.6-μm CMOS process. Thin-film resistors are used, and dynamic element matching (DEM) is applied to the 4-bit MSB to make sure that INL and DNL induced by random mismatch are within 0.5 LSB. Fig. 10 shows the SPICE simulation results of I ref, I aux, and I const. As can be seen, the variation of I const is 16 μa rather than the resolution of the AUXDAC (4 μa). It is due to the switch impedances. To make sure the switch impedances do not affect the transfer function of the R 2R ladder, the switch impedances need to be scaled up with a step of 2 from the MSB to the LSB. Therefore, the switch impedances become comparable with the value of R in the last several bits, making an impact on I ref. Since I aux is calculated based on the I ref model, if the I ref model is not precise, I const will see more variations.

5 660 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 62, NO. 7, JULY 2015 Fig. 10. SPICE simulation results of I ref, I aux, andi const in a (4+12)-bit segmented voltage-mode R 2R DAC. Fig. 12. SPICE simulation results of INL and DNL in a (4+12)-bit segmented voltage-mode R 2R DAC with 3σ resistor mismatch with R com =1 Ω ( =2.5 VandR =40kΩ). (a) Before current compensation at 27 C. (b) After current compensation at 27 C. (c) After current compensation at 125 C. Fig. 11. SPICE simulation results of after-compensation INL and DNL in a (4+12)-bit segmented voltage-mode R 2R DAC with (a) R com =1Ωand (b) R com =10Ω( =2.5VandR =40kΩ). Fig. 11(a) shows the SPICE simulation results of aftercompensation INL and DNL with R com =1Ω. Compared with Fig. 6(a), INL is reduced by six times from 1.7 to 0.27 LSB. Note that the essence behind the six-time INL reduction is that the code-dependent current is compensated, which is not related to the value of R com when R com R and does not affect the accuracy of the I ref model. This point is also verified by comparing Figs. 6(b) and 11(b). With R com =10Ω, INL decreases from 16.6 to 2.6 LSB, which is also a six-time reduction. To further validate the proposed technique s effectiveness, a 3σ resistor mismatch and temperature drift are added in the simulation, whose results are shown in Fig. 12. Since we apply DEM on the 4-bit MSB, it is very time consuming to run transient analysis for all 16-bit input codes. To reduce simulation time, only INL and DNL at 8-bit MSB codes are simulated, which still makes sense for process variations mainly affecting MSB precision. As shown in Fig. 12, before current compensation, INL is 1.6 LSB dominated by R com =1 Ω. After current compensation, INL is 0.4 LSB dominated by resistor mismatch. At 125 C, the proposed technique still works well with INL =0.43 LSB. The current compensation technique is estimated to take up 0.08 mm 2 and consume 0.06-mA average current. A buffer and a Gnd buffer good enough for a 16-bit DAC are estimated to have a 0.24-mm 2 area with a 0.3-mA quiescent current in the same process. Therefore, the proposed technique is estimated to take up 1/3 area and consume 1/5 power of the and Gnd buffers. Furthermore, 60% area comes from the purely digital computational block, which scales with the technology. For multichannel R 2R DACs, the computational block can be also shared among channels if time multiplexing is allowed. VI. CONCLUSION This brief has investigated the effect of the code-dependent reference current on the linearity of the voltage-mode R 2R DAC. An area- and power-efficient background reference current compensation technique is proposed to resolve the issue, which consists of a low-resolution AUXDAC and a purely digital computational block. Through dividing I ref in a segmented voltage-mode R 2R DAC to I MSB, I LSB, and I INT,this brief not only simplifies the I ref derivation but also efficiently implements the computational block. The simulation results of a(4+12)-bit segmented voltage-mode R 2R DAC verify the proposed technique with six-time INL reduction. Compared with the and Gnd buffers, the proposed technique is estimated to take up 1/3 area and consume 1/5 power. Due to its simplicity, the proposed technique can be easily redesigned in different processes. With 60% area coming from purely digital computational block, it will also become more competent with technology scaling and multichannel DACs. REFERENCES [1] D. Seo, A heterogeneous 16-bit DAC using a replica compensation, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp , Jul [2] R. C. McLachlan et al., A 20b clockless DAC with sub-ppm-inl 7.5nv/ Hz-noise and 0.05 ppm/ c-stability, IEEE J. Solid-State Circuits, vol. 48, no. 12, pp , Dec [3] D. Marche and Y. Savaria, Modeling R-2R segmented-ladder DACs, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp , Jan [4] X. Jiang, B. B. Nikjou, W. Khalil, and S. R. Naqvi, Differential digital-toanalog converter, U.S. Patent , Aug [5] R. Chandrasekaran and G. P. Vella-Colelro, Interpolation-based digital pre-distortion architecture, U.S. Patent , Nov. 4, [6] D. H. Sheingold, Analogue-Digital Conversion Handbook, 3rd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, [7] B. Holdsworth and R. C. Woods, Digital Logic Design, 4th ed. Oxford, U.K.: Newnes, 2002.