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1 University of Pittsburgh Experiment #7 Lab Report Analog-Digital Applications Submission Date: 08/01/2018 Instructors: Dr. Ahmed Dallal Shangqian Gao Submitted By: Nick Haver & Alex Williams Station #2 ECE 1212: Electronic Circuit Design Laboratory
2 Introduction The purpose of this experiment will be to design, implement, and test two types of digital-to-analog converters, and one analog-to-digital converter. Analog-digital conversion is useful in applications where computers, which process and communicate information in binary (digital) are interfacing with physical devices. These devices can include applications such as audio microphones or speakers, analog sensors such as pressure sensors or transducers, and motor controllers. Both digital-to-analog converters will be implemented using the 741 op-amp. This feature is particularly useful considering that digital signals are usually transmitted at lower voltages, which need to be amplified to be transmitted in the form of analog signals. The digitalto-analog converters both operate using a resistor network to weigh each bit according to its significance, and then combine the resulting voltages for a fraction of the digital operating voltage. The analog-to-digital converter will be implemented using a series of 339 voltage comparators. The analog input voltage will be connected to each comparator, which will output a logical 1 if the input voltage is greater than a given reference voltage. Using a range of reference voltages connected to the series of comparators, a finite level of resolution will be developed based on the number of comparators. Procedure Part I: R-2R Digital-to-Analog Converter In Part I, the 4-bit R-2R ladder digital-to-analog converter (DAC) in Fig. 1 was designed, implemented, and tested. In the prelab, Thevenin circuit reduction was used to determine output voltage as a function of the four input voltages. Figure 1: 4-Bit R-2R Network DAC with Inverting Amplifier The output voltage function in Eq. 1 confirms that the R-2R network weights input voltages as intended, with input V i3, the most significant bit, have two times the weight of V i2, four times the weight of V i1, and eight times the weight of V i0. As with other inverting amplifiers, resistors R and R f determine the voltage gain of the op-amp. V o = R f 3R [ 1 16 V i V i V i V i3] (1) Based on the specification that the analog output voltage be in the range of 0 to 3V, the voltage divider circuit in Fig. 2 was implemented with the R-2R network. The resistor network was connected to the (+) terminal of the op-amp to achieve a noninverted output. Considering that the specified output voltage range of the DAC was lower than the digital operating voltage of 5V, resistor R f was removed to form a voltage follower since no voltage amplification was needed.
3 Figure 2: 4-Bit R-2R Network DAC with Voltage Divider and Non-Inverting Amplifier A nominal value of R = 1 kω was chosen for the resistor network, and R y was calculated for the case of digital input B = 0001, meaning only the least significant bit was connected to V R = 5V. A linear fit of the entire 0 to 3V output range to each of the possible 16 digital input states results in an output voltage of V o = 0.2V for the case of B = For the circuit in Fig. 2, the voltage follower characteristic means that output voltage V o is equal to V +. Given this, Eq. 2 was used to determine R y = 5.33 kω. V o = V + = R y 3R + R y ( V R 16 ) (2) To test the digital-to-analog converter, a bit counter was connected to the four inputs of the converter. The counter was configured to count from 0000 to 1111 and repeat in a cyclical fashion. The counter was clocked using a pushbutton to change states as needed. With the counter and converter constructed, the counter output voltage was measured to be only 4.288V rather than the expected V R = 5V. Given this lower input voltage, R y was increased to 8.88 kω to maintain the 0 to 3V output voltage range. Pull-down resistor R x was chosen to be a nominal 10 kω. The 741 op-amp was connected to a supply voltage of V CC = ±15 V and the counter was connected to V PP = 5V. The counter was then cycled through each of the 16 states, and the corresponding output voltages were measured, as shown in Table 1. Output voltage was then plotted against input word, shown in Fig. 3, and a linear trendline was fitted to determine the offset voltage and linearity of the converter. Part II: Weighted Resistor Digital-to-Analog Converter In Part II, the 4-bit weighted resistor DAC in Fig. 4 was designed, implemented, and tested. Like the R-2R DAC, the resistor network was designed to weight input bits based on their significance. Figure 4: Weighted Resistor DAC with Non-Inverting Amplifier Like in Part I, Thevenin circuit reduction was used to determine the output voltage as a function of the input voltages. This output voltage function is given by Eq. 4.
4 V o = R f ( 1 R 1 V i0 + 1 R 2 V i1 + 1 R 3 V i2 + 1 R 4 V i3 ) (4) Resistor values were chosen so that the most significant bit at R 4 was weighted two times the bit at R 3, four times the bit at R 2, and eight times the bit at R 1. This resistor relationship is given by Eq. 5. R 1 = 2R 2 = 4R 3 = 8R 4 (5) Given Eq. 4, Eq. 5, a digital operating voltage of V R = 5V, and a specified output voltage range of -3 to 0V, the resistor values in Table 2 were chosen. Resistor Value R 1 8 kω R 2 4 kω R 3 2 kω R 4 1 kω R f 320 Ω Table 2: Resistor Values for Inverting Weighted Resistor DAC Like in Part I, a bit counter was used to test the DAC. Again, a decreased counter output voltage resulted in an unexpected output voltage range, so the value of R f was increased to 470 Ω to achieve the desired output voltage range. The counter and opamp were connected to supply voltages of ±15 V and 5 V, respectively, and the counter was used to cycle through each of the 16 digital input states. For each state, the output voltage was measured, as shown in Table 3. Output voltage was then plotted against input word, shown in Fig. 5, and a linear trendline was fitted to determine the offset voltage and linearity of the converter. Part III: Parallel Analog-to-Digital Converter In Part III, the parallel analog-to-digital converter (ADC) in Fig. 6 was designed, implemented, and tested. The ADC works by comparing the analog input voltage to a series of reference voltages using 339 differential comparators. A total of seven comparators were used, and references voltages equally divided the range of analog input voltage from 0 to 5V using a voltage dividing resistor network. Figure 6: Parallel ADC Using 339 Differential Comparators The limited number of comparators results in a finite resolution, meaning that a given range of analog input voltages will result in the same digital output. This resolution is outlined by the specification in Table 4. Input Voltage Range (Vin) a1 (MSB) a2 a3 (LSB) V V V V V V V V 1 1 1
5 Table 4: Input Voltage Resolution Specification for Parallel ADC The 339 differential comparator has open collector inputs. This means that when V + is less than V -, the output is connected to ground. When V + is greater than V -, however, the output is disconnected from ground and floating. This means that for a digital 1 to been seen by the combinational logic, V pp = 5V and a pull-up resistor must be connected to the comparator outputs. For Part III, a nominal value of 1 kω was chosen for the pull-up resistors. The purpose of the combinational logic circuits shown in Fig. 6 is to convert the 7 comparator outputs to a 3-bit binary number. The specification in Table 4 was used to determine the digital logic for each of the three output bits, shown in Eq. 6, 7, and 8. a 1 = i 4 (6) a 2 = i 2 i 4 + i 6 (7) a 3 = i 1 i 2 + i 3 i 4 + i 5 i 6 + i 7 (8) Based on these logic expressions for each output bit, it was determined that the combinational logic circuits could be constructed using three integrated circuits: Hex Inverter, Quad 2-Input AND, and Quad 2-Input OR. With the logic derived, the ADC in Fig. 6 was constructed and tested for functional operation. During construction, comparator outputs i 1 through i 7 were first tested to be functioning properly for a range of input voltages from 0 to 5V, generated by varying the programmable DC power supply. While working at lower input voltages, comparators were not functioning properly for input voltages near 5V. According to the 339 comparator datasheet, the IC requires a V cc at least 1.5V higher than the maximum input voltage. To account for this V cc was increased to 7V. Due to a limited number of power supplies, this 7V supply was also used for the voltage divider needed to establish comparator reference voltages. Therefore, the voltage divider was comprised of 1 kω resistors between the comparator inputs, and a 3.3 kω resistor from the 7V supply to the first input, giving the expected comparator reference voltages. With this adjustment made, the ADC functioned as expected, and output words were recorded for a variety of input voltages, as shown in Table 5. Next, the maximum operating frequency of the ADC was determined, both theoretically and experimentally. According to their datasheets, the logic gates have a maximum switching time of 22ns, while the comparators have a maximum settling time of 1.3µs. Based on the combinational logic, it was determined that a maximum of 4 logic gate changes could occur during a change of comparator states. This results in a maximum response time of 1388ns for each change of state. To determine the maximum frequency of a ramp signal voltage input, which could be used to test the ADC, the change of state time was multiplied by 8, to account for the total of 8 states the ADC would have during one ramp signal period. Therefore, a maximum ramp signal frequency of khz was determined. The function generator was connected to provide the input voltage of the ADC, a 0 to 5V ramp signal with a frequency of 90 khz. Because the least significant bit (a 3) changes states most frequently, its output was observed on the oscilloscope, shown in Fig. 7. The ramp signal frequency was then increased to 150 khz, and the corresponding a 3 output was observed, shown in Fig. 8. Lastly, a 0 to 5V square wave was connected as the input voltage. This was done to reduce the number of states from 8 to 2, either 0V or 5V. Theoretically, this would allow the ADC to respond 4 times faster, allowing for a maximum input signal frequency of 360 khz. A 0 to 5V square wave with this frequency was connected to the voltage input, and the most significant bit (a 1) was observed on the oscilloscope, shown in Fig. 9.
6 Vo (V) Results Part I Table 1 shows each digital input state for the R-2R DAC and its corresponding output voltage. Input Word (Decimal) Input Word (Binary) Output Voltage (V) Table 1: Input Word and Output Voltage for Non-Inverting R-2R DAC Fig. 3 shows output voltage as a function of input word, an approximately linear relationship Decimal W Figure 3: Output Voltage vs. Input Word for Non-Inverting R-2R DAC A linear trendline of Eq. 3 was added to Fig. 3. From Eq. 3, it was determined that the offset voltage of the converter was approximately 0.143V. A measure of the converter s linearity can be seen in the R 2 value of the trendline, equal to This indicates that the converter is mostly linear. V o = W V (3) Part II Table 3 shows each digital input state for the weighted resistor DAC and its corresponding output voltage. Input Word (Decimal) Input Word (Binary) Output Voltage (V)
7 Vo (V) Table 3: Input Word and Output Voltage for Inverting Weighted Resistor DAC Fig. 5 shows output voltage as a function of input word, a nearly perfect linear relationship Decimal W Figure 5: Output Voltage vs. Input Word for Inverting Weighted Resistor DAC A linear trendline of Eq. 6 was added to Fig. 5. From Eq. 6, it was determined that the offset voltage of the converter was V. A measure of the converter s linearity can be seen in the R 2 value of the trendline, equal to exactly 1. This indicates that the converter is almost perfectly linear. V o = W V (6) Part III Table 5 shows each digital output word for a series of input voltages applied to the ADC. Input Voltage (V) Output Word (Binary) Output Word (Decimal) Table 5: Input Word and Output Voltage for Inverting Weighted Resistor DAC
8 Figure 7: ADC Least Significant Bit ADC Output for 90 khz Ramp Signal Input Figure 8: Least Significant Bit ADC Output for 150 khz Ramp Signal Input Figure 9: Most Significant Bit ADC Output for 360 khz Square Wave Signal Input Discussion The testing of the converters that we designed yielded results that matched closely with expected values. As has been discussed in previous lab reports, the gain of op-amps is generally very close to expected values determined using ideal models. Because the only other components used in Part I were resistors, it is unsurprising that the results are near the theoretical prediction. In determining the maximum time delay for the DACs, it was discovered that the greatest delay occurred in changing from the 1111 state to the 0000 state. This is not surprising, as this state change requires the most state changes at the bit and transistor levels. The counter used to supply the DACs is organized in a cascading format, with state changes cascading from the least significant to the most significant bits.
9 Based on this counter topology, it was determined that counter response would be delayed at higher frequencies. This response delay would result in decreased relative linearity of the DAC output at higher frequencies. To determine the counter/dac time delay, an oscilloscope was used to observe the DAC output while the counter state was changed from 1111 to This resulted in an observed worst-case time delay of 5.2µs. As discussed in the Part III procedure, the comparators we were initially unable to operate in the case of input voltages closer to 5V. The modified circuit, with V cc increased to 7V, allowed for correct operation of the ADC for the complete range of expected input voltages. In calculating the expected maximum switching time of the ADC, datasheets for the combinational logic integrated circuits were used to determine a maximum logic gate switching time of 22ns. Based on the combinational logic, it was determined that a maximum of 4 logic gate changes could occur during a change of comparator states. Combined with the 1.3µs settling time of the comparators, a total maximum response time of 1388ns for each change of state was determined. With 8 state changes per input signal period, a frequency limitation of approximately 90 khz was established. Testing the circuit on the oscilloscope, it was observed that frequencies over 100kHZ generally caused increased digital output distortion caused by switch malfunction. Conclusion In Part I, Table 1 shows the output results from different inputs. The graphical representation of this in Fig. 3 shows that the output creates a near linear relationship. The small differences that do exist are most likely due to the tolerances in the resistors, as there are no outliers in the data. Results observed in Part II were similar to those in Part I, except the DAC was implemented as a weighted resistor circuit. In this case, Fig. 5 shows the trendline drawn from the data, which was a nearly perfect linear fit, resulting in linear regression R 2 value of nearly 1. Again, any small variances that did exist can be explained by resistor tolerances. In general, the implemented circuits functioned excellently, and the op-amp portion of the converters performed almost ideally. The results from Part III are shown in Table 5, which indicate that the ADC tested in Part III output the expected results for each test case. This indicates that the circuit was designed and built correctly. The comparators functioned without error once they had the proper supply voltage given the maximum 5V comparison voltage. Additionally, none of the gate transistors created any issues during testing, which is a marked difference from previous labs involving MOSFETs and BJTs. Fig. 7 shows where the maximum expected before the circuit was no longer able to function effectively. Fig. 8 and Fig. 9 highlight this point, showing the increasing noise observed at higher frequencies. References Dr. Ahmed Dallal s ECE 1212 Lecture Notes Texas Instruments ua741 General-Purpose Operational Amplifier Data Sheet Texas Instruments 74LS93 4-Bit Binary Counter Datasheet Texas Instruments LM339 Quad Differential Comparator Data Sheet
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