2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS

Transcription

1 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS November 30 - December 3, 2008 Venetian Macao Resort-Hotel Macao, China IEEE Catalog Number: CFP08APC-USB ISBN: Library of Congress: IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. For CD-ROM technical questions contact: Alliance Management Group, LLC info@amg-corp.com Phone:

2 A Low Offset Rail-to-Rail 12b 2MS/s 0.18µm CMOS Cyclic ADC Young-Ju Kim (1), Hee-Cheol Choi (1), Pil-Seon Yoo (1), Dong-Suk Lee (1), Joong-Ho Choi (2), Seung-Hoon Lee (1) (1) Dept. of Electronic Engineering, Sogang University, #1 Sinsoo-Dong, Mapo-Gu, Seoul, , Korea (2) Dept. of Electrical and Computer Engineering, University of Seoul, Jeonnong-Dong, Dongdaemun-Gu, Seoul, Korea Abstract - A 12b 2MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18mm CMOS technology demonstrates the effective number of bits of for a 100kHz full-scale input at 2MS/s. The ADC with an active die area of 0.12mm² consumes 3.6mW at 2MS/s and 3.3V(analog)/1.8V (digital). I. INTRODUCTION Highly efficient analog-to-digital converters (ADCs) based on delta-sigma modulator, successive approximation register (SAR), and cyclic architectures have been commonly employed for audio and sensor applications such as voice recoding circuits, touch screen, power management units (PMU), battery measurement systems, and micro electro mechanical systems (MEMS) operating at a several hundreds of ks/s to several MS/s [1]. Of those applications, many researches have been carried out to reduce the offset voltages of ADCs, particularly in X-Y position converters for a touch screen interface used to gauge the precise voltages of sensing nodes and battery fuel gauge systems [2]. The reference voltage offset errors are caused by device mismatches in a differential input pair of operational amplifiers (op-amps) and passive or active elements for a reference voltage generator with gain errors of an input sample-and-hold amplifier (SHA). In addition, one of the main offset sources in single-ended signal applications comes from the mismatch of a common mode voltage (VCOM) applied to the complementary input of a differential op-amp converting a single-ended input signal to a differential output signal. This work proposes a SHA-free input sampling scheme and a passive device-free voltage reference scheme, reducing top and bottom reference offsets without additional offset cancellation and trimming circuits [2], [3]. II. PROPOSED ADC ARCHITECTURE AND CIRCUIT IMPLEMENTATION A. ADC Architecture The proposed 12b 2MS/s ADC based on a two-stage (2.5- bits/stage) cyclic architecture consists of two multiplying D/A Fig. 1. Proposed ADC and reference scheme. converters (MDACs), two flash ADCs, a reference current generator, a clock generator, and digital correction logic (DCL), as shown in Fig. 1. The two-stage based cyclic architecture shows a relatively optimized power dissipation and reasonable chip area at a sampling rate of several MS/s. The proposed cyclic ADC needs 3 clock cycles to produce a full single 12b binary output corresponding to an analog input. In the proposed cyclic ADC, the front-end MDAC with a high DC gain samples a single-ended input signal instead of an extra SHA [4]. It greatly reduces the offset error from a finite DC gain of the SHA, while minimizing power consumption and improving signal-to-noise ratio (SNR). Analog functional circuit blocks are designed with 3.3V devices employing thick-gate oxide while the clock generator and DCL are optimized with 1.8V devices based on thin-gate oxide to reduce chip area. Digital level shifters with a crosscoupled architecture are located in the interface between 3.3V and 1.8V circuit blocks. B. Low-Offset MDAC1 In conventional ADCs, two reference voltages, REFT and REFB, are generated approximately at 3/4 and 1/4 levels of a full-scale signal along with offset errors caused by passive or active element mismatches in the internal voltage generator [5]. On the other hand, the proposed MDACs employ two reference voltages of VRT and VRB, corresponding to the maximum and minimum voltage levels of a full-scale input signal, respectively, as illustrated in Fig. 1. For a rail-to-rail input signal, VRT and VRB are connected to two power supplies, VDD and GND. There is no passive or active device in the reference voltages for the MDAC, which affects the /08/$ IEEE. 17

3 TABLE I MDAC CAPACITOR ARRAY CONNECTION DURING RESIDUE VOLTAGE AMPLIFICATION. Fig. 2. Schematic of the proposed MADC1 with the front-end AMUX. accuracy of the ADC. Inaccurate reference voltages, REFT and REFB, produced from a resistor string, are used only for the sub-ranging flash ADCs in the proposed cyclic ADC. Fig.2 shows a sampling scheme of the MDAC1 with the front-end analog MUX (AMUX). The proposed voltage reference scheme reduces the ADC power consumption by increasing a feedback factor compared to the conventional design, which has extra capacitors not used for an input sampling. During the input sampling mode, the upper capacitor array samples an input signal, VIN, while the lower capacitor array samples reference voltages, VRT and VRB, instead of VCOM, as a reference voltage for a single-ended input. The proposed input sampling network reduces offset errors caused by a common-mode-voltage sampling scheme in the conventional MDACs. During the next amplification mode, Fig. 3. Proposed two-stage switched op-amp. the MDAC1 amplifies a residue voltage, which is the difference between a sampled input and a reconstructed analog signal from a digital code of the flash ADC. The residue voltage amplifying procedure in Fig. 2 is described in Table I. C. Two-Stage Switched OP-AMP The MDAC1 and MDAC2 employ a two-stage amplifier to achieve a DC gain and output swing margin sufficient for 12b accuracy as shown in Fig. 3. The folded-cascode architecture with an NMOS input pair in the first stage amplifier primarily achieves a high DC gain while the common-source architecture with a tail current source in the second stage amplifier obtains a high output swing. The two- 18

4 Fig. 4. Die photo of the proposed ADC. Fig. 6. Measured FFT plot (f IN = 100kHz and f S = 2MS/s). Fig. 5. Measured DNL and INL. stage op-amp performs an offset cancellation with a closedloop sampling technique [6]. During the sampling mode, the input nodes (INT and INC) and first stage output nodes (OT1 and OC1) are connected in a unity-gain feedback by the switch transistors of M1 and M2. At the same time, two compensation capacitors are disconnected by the switch transistors of M3 and M4 to overcome the bandwidth reduction of the closed-loop sampling scheme. Moreover, the proposed two-stage op-amp adopts the cascoded compensation and switched op-amp power-reduction techniques simultaneously to reduce power consumption and active area [7], [8]. III. MEASURED PERFORMANCES The prototype two-stage cyclic ADC is designed and implemented in a 0.18µm single-poly six-metal CMOS process. It consumes 3.6mW at an 8MHz clock required for a Fig. 7. Measured SNDR and SFDR. 2MS/s conversion rate with 3.3V and 1.8V power supplies used for analog and digital circuit blocks, respectively. The active die area is 0.12mm² (=330µm 365µm), as shown in Fig. 4. As illustrated in Fig. 5, the measured differential non-linearity (DNL) and integral non-linearity (INL) are within ±0.25LSB and ±0.69LSB, respectively. At a conversion rate of 2MS/s, the measured signal-to-noise-anddistortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 70.9dB and 81.7dB, respectively, with a 100kHz and 3.3Vp-p input signal, as shown in Fig. 6. The SNDR and SFDR of Fig. 7 are measured with increasing input frequencies at a sampling frequency of 2MS/s. As shown in Fig. 7, the prototype ADC maintains a SNDR and SFDR of over 70dB and 80dB with input frequencies increased to 200kHz. The prototype cyclic ADC with the proposed reference scheme achieves low top and bottom offset errors of 0.77LSB and 0.35LSB, respectively, which are less than 1mV. The overall ADC performance is summarized in Table II. 19

5 TABLE II PERFORMANCE SUMMARY OF THE PROTOTYPE ADC IV. CONCLUSION This work proposes a low-offset rail-to-rail 12b 2MS/s cyclic and pipeline ADC for audio and sensor application systems. The propose ADC shows a measured DNL and INL of ±0.25LSB and ±0.69LSB, and achieves low top and bottom offset errors of 0.77LSB and 0.35LSB levels with a single-ended 3.3Vp-p analog input signal. The prototype ADC shows a power consumption of 3.6mW with an active die area of 0.12mm 2. ACKNOWLEDGEMENTS This work was supported by the IDEC of KAIST and "System IC 2010" project of Korea Ministry of Knowledge Economy. REFERENCES [1] Y. Yang, T. Sculley, and J. Abraham, A single die 124dB stereo audio delta sigma ADC with 111dB THD, in Proc. European Solid-State Circuits Conf., pp , Sept [2] P. G. Blanken and S.E.J. Menten, A 10µV-Offset 8kHz Bandwidth 4 th - Order Chopped SD A/D Converter for Battery Management, in ISSCC Dig. Tech. Papers, pp , Feb [3] M. Furuta, S. Kawahito, T. Inoue, Y. Nishikawa, A cyclic A/D converter with pixel noise and column-wise offset cancellation for CMOS image sensors, in Proc. European Solid-State Circuits Conf., pp , Sept [4] H. C. Choi, S. B. You, H. Y. Lee, H. J. Park, and J. W. Kim, A calibration-free 3V 16b 500kS/s 6mW 0.5mm 2 ADC with 0.13um CMOS, in Symp. VLSI Circuits Dig. Tech. Papers, pp , June [5] Y. J. Cho and S. H. Lee, "An 11b 70 MHz 1.2 mm 2 49 mw 0.18 um CMOS ADC with On-Chip Current/Voltage References," IEEE Trans. Circuits Syst. I, vol. 52, no. 10, pp , Oct [6] S. C. Lee, K. D. Kim, J. K. Kwon, J. D. Kim, and S. H. Lee, "A 10bit 400MS/s 160mW 0.13um CMOS Dual-Channel Pipeline ADC Without Channel Mismatch Calibration," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp , July [7] B. Ahuja, An Improved Frequency Compensation Technique for CMOS Operational Amplifiers, IEEE J. Solid-State Circuits, vol. 18, no. 6, pp , Dec [8] H. C. Kim, D. K. Jeong, and W. C. Kim, A 30mW 8b 200MS/s Pipelined CMOS ADC Using a Switched-Opamp Technique, in ISSCC Dig. Tech. Papers, pp , Feb