Power (mw) DNL/INL (LSB) 200k / / /
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1 동부하이텍공정 IP LIST 서강대학교집적회로설계연구실 IP fsample (MS/s) VDD (V) Power (mw) / (LSB) Area (mm 2 ) Process (um) Comments [1] 12-bit ADC [2] 12-bit ADC [3] 10-bit ADC [4] 15-bit ADC [5] 13-bit ADC 200k / / / / / IEICE Trans. Feb AICSP Feb IEEE CICC Sept IET Letters Oct IEICE Trans. Sept [6] 10-bit ADC_V4 [7] 12-bit ADC_V1 [8] 12-bit ADC_V2 [9] 12-bit ADC_V / Best Specs / Best Specs / Best Specs / Best Specs 1
![[1] A 12b 200kHz 0.52mA 0.47mm2 Algorithmic ADC for MEMS 12b 200kHz Supply Voltage 1.8V 0.94mW ±0.40LSB ±1.97LSB 0.6mm x 0.](/docs-images/86/93993682/images/2-0.jpg "78mm (MS180BB_Rev1p3) Young-Ju Kim, Hee-Cheol Choi, Seung-Hoon Lee, and Dongil \"Dan\" Cho, \"A 12b 200kS/s 0.52mA 0.47mm2 Algorithmic A/D Converter for MEMS Applications,\" IEICE Trans.")
2 [1] A 12b 200kHz 0.52mA 0.47mm2 Algorithmic ADC for MEMS 12b 200kHz Supply Voltage 1.8V 0.94mW ±0.40LSB ±1.97LSB 0.6mm x 0.78mm (MS180BB_Rev1p3) Young-Ju Kim, Hee-Cheol Choi, Seung-Hoon Lee, and Dongil "Dan" Cho, "A 12b 200kS/s 0.52mA 0.47mm2 Algorithmic A/D Converter for MEMS Applications," IEICE Trans. on Electronics, vol. E91-C, No. 2, pp , Feb
![[2] A 12b 130MS/s 108mW 1.8mm2 0.18um CMOS ADC 12b 130MHz Supply Voltage 1.8V 108mW ±0.69LSB ±2.12LSB 1.37mm x 1.](/docs-images/86/93993682/images/3-0.jpg "28mm (MS180BB_Rev1p3) Hee-Cheol Choi, Young-Ju Kim, Woo-Joo Kim, Younglok-Kim, and Seung-Hoon Lee, \"A 10b 120MS/s 108mW 0.")
3 [2] A 12b 130MS/s 108mW 1.8mm2 0.18um CMOS ADC 12b 130MHz Supply Voltage 1.8V 108mW ±0.69LSB ±2.12LSB 1.37mm x 1.28mm (MS180BB_Rev1p3) Hee-Cheol Choi, Young-Ju Kim, Woo-Joo Kim, Younglok-Kim, and Seung-Hoon Lee, "A 10b 120MS/s 108mW 0.18um CMOS ADC with a PVT-insensitive current reference," Analog Integrated Circuits and Signal Processing, vol 58, no. 2, pp , Feb
![[3] A 10b 25MS/s 0.8mm2 4.9mW 0.13um CMOS ADC 10b 25MHz Supply Voltage 1.2V 4.9mW ±0.43LSB ±0.97LSB 0.67mm x 1.21mm 0.](/docs-images/86/93993682/images/4-0.jpg "13um Dongbu CMOS (MS130SA_Rev1p3) Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Young-Deuk Jeon, Seung-Chul Lee, and Jong-Kee Kwon, \" A 10b 25MS/s 4.8mW 0.")
4 [3] A 10b 25MS/s 0.8mm2 4.9mW 0.13um CMOS ADC 10b 25MHz Supply Voltage 1.2V 4.9mW ±0.43LSB ±0.97LSB 0.67mm x 1.21mm 0.13um Dongbu CMOS (MS130SA_Rev1p3) Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Young-Deuk Jeon, Seung-Chul Lee, and Jong-Kee Kwon, " A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications," Custom Integrated Circuits Conference (CICC) 2006, San Jose, California, pp , Sept
![[4] A Digitally Calibrated 15b 50MS/s 140mW 4.2mm2 ADC 15b 50MHz Supply Voltage 1.8V 140mW ±0.80LSB ±5.52LSB 2.58mm x 1.](/docs-images/86/93993682/images/5-0.jpg "64mm (MS180BB_Rev1p3) Kyung-Hoon Lee, Young-Ju Kim, Kwang-Soo Kim, and Seung-Hoon Lee, \"14b 50MS/s 0.")
5 [4] A Digitally Calibrated 15b 50MS/s 140mW 4.2mm2 ADC 15b 50MHz Supply Voltage 1.8V 140mW ±0.80LSB ±5.52LSB 2.58mm x 1.64mm (MS180BB_Rev1p3) Kyung-Hoon Lee, Young-Ju Kim, Kwang-Soo Kim, and Seung-Hoon Lee, "14b 50MS/s 0.18um CMOS Pipeline ADC Based on Digital Error Calibration," IET (The Institution of Engineering and ) Electronic Letters, vol. 45, pp , Oct
![[5] A 13b 100MS/s 42mW 1.22mm2 0.13um CMOS ADC 13b 100MHz Supply Voltage 1.2V 42mW ±0.70LSB ±1.79LSB 1.34mm x 0.91mm 0.](/docs-images/86/93993682/images/6-0.jpg "13um Dongbu CMOS (MS130SA_Rev1p8) Young-Ju Kim, Kyung-Hoon Lee, Myung-Hawn Lee, and Seung-Hoon Lee, \"A 0.31pJ/conversion-step 12-bit 100MS/s 0.")
6 [5] A 13b 100MS/s 42mW 1.22mm2 0.13um CMOS ADC 13b 100MHz Supply Voltage 1.2V 42mW ±0.70LSB ±1.79LSB 1.34mm x 0.91mm 0.13um Dongbu CMOS (MS130SA_Rev1p8) Young-Ju Kim, Kyung-Hoon Lee, Myung-Hawn Lee, and Seung-Hoon Lee, "A 0.31pJ/conversion-step 12-bit 100MS/s 0.13um CMOS A/D Converter for 3G Communication Systems," IEICE Trans. on Electronics, vol. E92-C, no. 9, pp , Sept
![[6] A 10b 100MS/s 24.2mW 0.80mm2 0.18um CMOS ADC V4 Supply Voltage Chip Description 10b 100MHz Analog : 1.8V, Digital : 1.2~1.8V 24.2mW ±0.58LSB ±0.94LSB 1.08mm x 0.](/docs-images/86/93993682/images/7-0.jpg "74mm (MS180BB_Rev2p1) Single two-stage op-amp sharing based on switched op-amp in MDACs Kyung-Hoon Lee, Se-Won Lee, Young-Ju Kim, Kwang-Soo Kim, and Seung-Hoon Lee, \"Ten-bit 100 MS/s 24.2 mw 0.")
7 [6] A 10b 100MS/s 24.2mW 0.80mm2 0.18um CMOS ADC V4 Supply Voltage Chip Description 10b 100MHz Analog : 1.8V, Digital : 1.2~1.8V 24.2mW ±0.58LSB ±0.94LSB 1.08mm x 0.74mm (MS180BB_Rev2p1) Single two-stage op-amp sharing based on switched op-amp in MDACs Kyung-Hoon Lee, Se-Won Lee, Young-Ju Kim, Kwang-Soo Kim, and Seung-Hoon Lee, "Ten-bit 100 MS/s 24.2 mw 0.8 mm μm CMOS pipeline ADC based on maximal circuit sharing schemes," IET (The Institution of Engineering and ) Electronic Letters, vol. 45, pp , Dec
![[7] A 12b 50MS/s 28.6mW 1.09mm2 0.18um CMOS ADC with a Variable Gain Amplifier_V1 12b 50MHz Supply Voltage 1.8V 28.6mW ±0.26LSB ±0.75LSB Input Voltage MAX : 2.](/docs-images/86/93993682/images/8-0.jpg "1Vp-p, MIN : 1.5Vp-p VGA Dynamic Range -3dB ~ 0dB VGA Gain Step -0.2dB 1.25mm x 0.")
8 [7] A 12b 50MS/s 28.6mW 1.09mm2 0.18um CMOS ADC with a Variable Gain Amplifier_V1 12b 50MHz Supply Voltage 1.8V 28.6mW ±0.26LSB ±0.75LSB Input Voltage MAX : 2.1Vp-p, MIN : 1.5Vp-p VGA Dynamic Range -3dB ~ 0dB VGA Gain Step -0.2dB 1.25mm x 0.87mm (MS180BB_Rev2p1) Chip Description VGA based on digital C-segment combination 8
![[8] A 12b 50MS/s 28.1mW 1.09mm2 0.18um CMOS ADC with a Variable Gain Amplifier_V2 12b 50MHz Supply Voltage 1.8V 28.1mW ±0.41LSB ±0.63LSB Input Voltage MAX : 2.](/docs-images/86/93993682/images/9-0.jpg "1Vp-p, MIN : 1.5Vp-p VGA Dynamic Range -3dB ~ 0dB VGA Gain Step -0.2dB 1.25mm x 0.")
9 [8] A 12b 50MS/s 28.1mW 1.09mm2 0.18um CMOS ADC with a Variable Gain Amplifier_V2 12b 50MHz Supply Voltage 1.8V 28.1mW ±0.41LSB ±0.63LSB Input Voltage MAX : 2.1Vp-p, MIN : 1.5Vp-p VGA Dynamic Range -3dB ~ 0dB VGA Gain Step -0.2dB 1.25mm x 0.87mm (MS180BB_Rev2p1) Chip Description VGA based on approximated log function with merged Cs 9
![[9] A 12b 100MS/s 19.3mW 0.92mm2 0.13um CMOS ADC V2 12b 100MHz Supply Voltage 1.0V 19.3mW ±0.44LSB ±1.53LSB 0.91mm x 1.01mm 0.13um Dongbu CMOS (1233MC13SA_Rev2p0.1) 1.](/docs-images/86/93993682/images/10-0.jpg "SHA-free architecture 2. Single two-stage op-amp sharing based Chip Description on switched op-amp in MDACs 3.")
10 [9] A 12b 100MS/s 19.3mW 0.92mm2 0.13um CMOS ADC V2 12b 100MHz Supply Voltage 1.0V 19.3mW ±0.44LSB ±1.53LSB 0.91mm x 1.01mm 0.13um Dongbu CMOS (1233MC13SA_Rev2p0.1) 1. SHA-free architecture 2. Single two-stage op-amp sharing based Chip Description on switched op-amp in MDACs 3. Two-step operation of FLASH3 ADC based on two-stage preamp 10
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