Gunadarma University, Jl. Margonda Raya 100, Depok, Jawa Barat 16424, Indonesia

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1 Advanced Materials Research Online: ISSN: , Vol. 646, pp doi: / Trans Tech Publications, Switzerland A 8-bit DAC Design in AMS 0.35 μm CMOS Process for High-Speed Communication Systems Veronica Ernita Kristianti a, Hamzah Afandi b, Eri Prasetyo Wibowo c, Djoko Purnomo d Gunadarma University, Jl. Margonda Raya 100, Depok, Jawa Barat 16424, Indonesia a veronica@staff.gunadarma.ac.id, b hamzah@staff.gunadarma.ac.id, c eri@staff.gunadarma.ac.id, d jokopurn@staff.gunadarma.ac.id Keywords: CMOS, DAC (Digital-to-Analog Converter), Operational Amplifier (Op-Amp), and MOS Switch. Abstract. DAC architecture that is designed in this research can be applied in high-speed communication systems. DAC architecture that is presented in this research is based on the R2R ladder method. The design requires three main components, namely switches, resistors, and opamp. This method has been applied to the 8-bit DAC for high-speed communication system using AMS technology 0.35 μm CMOS process. Resistors that are used in R2R DAC is replaced by transistors, so that the size is smaller and easier layout in the manufacturing process. Mentor graphics software is used as a simulator of the design. DAC design with 8-bit resolution in this research can be applied to the speed up to 1000 Msps. In the way the design can be categorized as high-speed DAC that can be used in a communication system. Introduction High-speed DAC is the most important element in the communication system. As an example, applications system such as very high-data rate digital subscriber line (VDSL), wireless local area network (WLAN), global mobile for mobile telecommunication (GSM) requires DAC on-chip highspeed high-resolution based on the same CMOS process as digital circuit combined together to produce a low power, small chip area, and high-speed performance [1]. Another example is the cable modem. Cable modem system consists of many channels, where each channel contains of digital modulation and DAC. Digital modulation in each channel, for example, quadrature amplitude modulation (QAM) or quadrature phase shift keying (QPSK). Without DAC high-speed and high-resolution, these modulation functions must be implemented in the analog domain, which generally result in relatively poor quality signal [2]. DAC has four main topologies that can be used in the design to produce a component of high-speed, high-resolution, and low power. The four topologies are binary weighted DAC, R2R ladder DAC, delta-sigma DAC, and segmented DAC. Binary Weighted DAC, these DAC consist of either current sources or resistors for each bit. These elements are connected to a summing point which provides the output. R2R Ladder DAC, these DAC consist of a structure of resistor values which can be closely matched. This topology is binary weighted and can provide a higher resolution compared to its purely binary weighted counterpart. Delta-Sigma DAC, these DAC are relatively new and they rely on pulse density and noise shaping techniques which allow for the use of a lower resolution DAC in the forward path (usually 1 bit). Segmented DAC, these DAC are a hybrid between the binary weighted and the thermometer decoded topologies. This mix proved to be the fastest and most precise topology, at the expense of die area [3]. Based on the architecture of the DAC, DAC needed a lot of operational amplifier (op-amp) as the switching capacitor and the sampling-hold. It would require the operational amplifier (op-amp) which has open-loop amplifier (AoL), gain bandwidth (GBW) and power consumption, using PMOS and NMOS components to be applied to the DAC. Specifications of the selected DAC are the R2R ladder DAC. With these types to meet the specifications of the op-amp with CMOS technology, is required open-loop amplifier (AoL) minimum of 60 db and gain bandwidth of 159 All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-08/04/16,22:48:14)

2 Advanced Materials Research Vol MHz. DAC design is designed for a communication system that has a high-speed, so DAC speed should be between Msps with voltage input 3.3 V [4]. DAC is designed for 8-bit resolution with AMS technology 0.35 μm using mentor graphics tools. Related Work Fig. 1: High Speed DACs [4] The four main topologies owned DAC has been widely used as a reference in designing DAC highspeed high-resolution. As the binary weighted DAC, presented in [1], DAC is designed for applications of high-speed communication systems. The design is made with a resolution of 12 bits and input voltage 3 V. Results obtained from the draft, obtained DAC which has a speed of 100 MS/s. DAC is processed by 0.35 μm CMOS technology. Designs are grouped into two groups, namely binary-weighted array and current unit-cells matrix. The choice of architecture for binaryweighted array operates at high speed and doesn t need the separate decoders driving the current cells. However, this architecture is very sensitive to variation process and has high glitch energy. While the current-matrix cells have low glitch energy and better in terms of minimizing the number of switched current cells at code transition. Thus the two are coordinated to produce a DAC highspeed that can be applied to the communication system. Binary weighted is also used in the design of 10-bit DAC [5]. DAC is designed using 0.18 μm CMOS technology and the input voltage is 1.8 V. The design obtained from a previous study of the comparison between the converter unaryweighted and binary-weighted, where it was said that the boundary between the decoder and the latch is important to indicate the presence of both analog and digital signals. These problems can be overcome by increasing the capacitance at that node and making all buffer-latch structures identical. Thus for that they have to design the modeling of binary-weighted DAC that has high dynamic performance. The result of the design is the sample rate of 250 MS/s. There is a certain code of spectral behavior that is identical to the one of a highly segmented converter. In this code, the performance is not improved. The binary nature of the converter thus did not pose limits to the SFDR. The performance drop while operating the device far outside the nominal operating point was limited, showing that the accuracy in the latch can be traded with speed. Design DAC for high-speed system application is also described in [6]. DAC design is mainly used in high-speed Direct Digital Frequency synthesizers (DDFS) modem communication system. Its aim is to design a high performance DAC without trimming based on the 0.35 μm CMOS platform. The proposed DAC consists of a current-cell matrix unit and a binary-weighted array to obtain high linearity at the level of 12 bits. To increase the linear that can be degraded by nonlinear symmetric errors and degraded by two-dimensional error in the DAC, use a novel switching scheme called Q 2 random walk. Various layout techniques are also used simultaneously to improve the performance of static and dynamic. Update rate derived from the design of 300 MHz with an input voltage 3.3 V. In addition to the binary-weighted, segmented DAC is also used to design high-speed DAC. The methodologies presented in [7], in which the design is applied to the DAC with 12-bit resolution and generate a rate of 400 MHz. The research was conducted with the aim to complement previous approaches in terms of sizing and sequencing methodology design for highspeed high accuracy current steering DAC, and avoids the introduction of safety margins for arbitrary saturation voltage overdrive conditions by analyzing the effects of process variations in the operating of all the transistors of the current cell. Operational amplifier (op-amp) on the design is used as a switching capacitor process and sampling-hold. Presented at the [8], the figure 2 represents the electronic schematic of the column amplifier. The design of this amplifier provides low impedance for the column lines, converts the

3 180 Advanced Technologies in Nano Materials and Electric Devices readout current from the selected pixel into a voltage that is proportional to the integrated photo voltage in the pixel. The concept of using current mirror amplifier column is to amplify signal by duplication at the column level. Amplification is achieved by designing a current mirror m 20 and m 24 with ratio W/L m20 = n W/L m24. Fig. 2: Column amplifier schematic [8] The transistors m 22 and m 23 are added to enhance the output impedance of the current mirror. The circuit including m 17, m 18, and m 20 operates almost identically to a diode connected transistor; it is used to ensure that all the transistors bias voltages are matched to the output side (m 22, m 23, m 24 ). The transistors m 17, m 21 are used to bias the feedback circuit. The transistors m 26, m 27, m 28, m 29, m 30 make up a differential unity gain amplifier. Once the current signal has been amplified by column current mirror amplifier, its output is suitable for any subsequent current mode image processing, either in continuous time or integration mode. In our case, these outputs will be used as inputs for the feature extracting architecture dedicated to the mean evaluation of consecutive pixels. In this research, the DAC resistor will be replaced by the transistor, since the research was conducted based on CMOS technology which consists of NMOS and PMOS transistors. Change resistor with transistor; the aim is to minimize the size of the layout design which will affect the cost of production of this DAC design. In addition, ease in applying the design into a chip to be manufactured and marketed later. Design of the Digital to Analog Converter Just as its functions, DAC or digital to analog converter is to change the digital signal into an analog signal. For that, DAC input is given in the form of binary numbers. Given input will go through the switch, which switches designed from two transistors; NMOS and PMOS. The working principle of the switch, as described previously, if the input given 0 then NMOS transistor in open conditions and PMOS transistors in the closed condition so VDD voltage will pass through that transistor type P and output value is 1. Conversely, if the input is 1 then the PMOS transistors in the NMOS transistor open condition and a closed condition so the voltage from ground will pass through transistor type N and the output circuit value is 0 [9]. The output of each switch will pass resistor of R2R ladder topologies. R2R ladder DAC is comprised of structures resistor values that can be matched. Elements connected to the summing point of the output. The results of the summing point and then go to op-amp with a positive voltage (VPOS). In the DAC, the operational amplifier is very important to get results with a good accuracy.

4 Advanced Materials Research Vol Fig. 3: Op-Amp circuit Operational amplifiers are designed with VDD = 3.3V and VSS = -3.3V, the value of the load capacitor is 0.2 pf. Operational amplifier consists of constant current source is M_9 and M_10. This reference current will be reflected in two current sources that will be used in the differential amplifier and the output amplifier. Transistors M_8, M_9, M_10 work as current mirrors. Transistor M_1, M_2, M_3, M_4 is differential amplifier, which will measure the difference between the input voltage VNEG and the input voltage VPOS. Transistor is a part of M_5 output amplifier. Capacitors are used for negative feedback path. Its function is to add the existing Miller effect due to the presence of the capacitor. This addition will cause the op-amp with a dominant pole. It will cause the op-amp works in stable condition, so it would not to cause Oscillation. In addition to getting a high speed DAC can be applied in a communications system, another goal of this research is to change the resistor used is R2R ladder DAC method with transistor. Resistor values are replaced by transistors conducted by the following equation The design that has been changed then simulated using mentor graphics software on a standard AMS technology 0.35 μm CMOS process. (1) Fig. 4: Diagram Block DAC Circuit Each blocks consisting of 16 transistors on MOS switch, 16 transistors on R2R ladder, 10 transistors and one capacitor in the op-amp. Measurement Results The simulation that was conducted first is to design an op-amp. This is done with a purpose, a series of op-amp has been designed to meet the requirements can be applied in the design of the DAC as capacitor switching and sampling-hold. The simulation results show that op-amp produces an open loop amplifier (AOL) of 63.9 db with a gain bandwidth of MHz.

5 182 Advanced Technologies in Nano Materials and Electric Devices Fig. 5: Simulation Results of Amplification AoL, GBW, and PM Op-Amp Thus the op-amp circuit is applied to the circuit DAC with R2R ladder method. Reference voltage (V REF ) given on the simulation of 1.5 V, the input in the form of binary number with 8-bit resolution. Table 1: The Value of Analog Voltage with V REF 1.5 V Based on the Simulation D7 D6 D5 D4 D3 D2 D1 D0 V out This circuit can be applied to speed up to 1000 Msps. Based on these results; the design DAC can be categorized as DAC that can be used for high-speed communication systems. Stage DAC layout was estimated to occupy about 221 μm x 96 μm. From design layout and specifications that have been generated, then the fabrication process can be done. This layout can be made into a single chip or grown in an apparatus (Embedded System) as required. In this research the layout is includes a chip (System on Chip) that is connected to the pins according to the function of each pin as shown in Fig. 6. Conclusion Fig. 6: System on Chip DAC is designed for high-speed communication system, designed using AMS technology 0.35 um CMOS process. With a resolution of 8-bit 3.3 V input voltage, this design can achieve speeds up to 1000 Msps. Based on these results, the DAC can be categorized as high-speed designs that can be used for communication systems. The use of resistors on a system that requires a large space, will affect the cost of production, this alone raises the thought to look for alternatives in order to minimize the use of space in this DAC design. An alternative in this research is to replace the use of resistors in the DAC circuit using NMOS transistors, as this has been successfully done. Based on research data, the circuit using a resistor DAC and using NMOS transistors showed no significant difference, so the use of a transistor can be used instead of the use of resistors.

6 Advanced Materials Research Vol References [1] Min-Jung Kim, Hyuen-Hee Bae, Jin-Sik Yoon, and Seung-Hoon Lee, A 3 v 12b 100 MS/s CMOS D/A Converter for High-Speed Communication Systems, Semiconductor Technology and Science, vol. 3, pp , December [2] Chi-Hung Lin, Klaas Bult. A 10-b, 500-MSample/s CMOS DAC in 0.6 mm 2, IEEE Solid- State Circuits, vol. 33, pp , December [3] Taoufiq Bellamine, 8 Bit Current Steering DAC, May [4] Maxim, High-Speed ADCs, DACs, and AFEs. Maxim Integrated Products, Inc, September [5] Jurgen Deveugele, Michiel S. J. Steyaert, A 10-bit 250-MS/s Binary-Weighted Current- Steering DAC, IEEE Solid-State Circuits, vol. 41, pp , February [6] Weining Ni,Xueyang Geng,Yin Shi, Foster Dai, A 12-bit 300 MHz CMOS DAC for Highspeed System Applications, IEEE, pp , [7] Miquel Albiol, José Luis González, Eduard Alarcón, Improved Design Methodology for High- Speed High-Accuracy Current Steering D/A Converters, IEEE, [8] Dominique GINHAC, Eri Prasetyo, Michel Paindavoine, Barth el emy Heyrman, Principles of A CMOS Sensor Dedicated To Face Tracking and Recognition, IEEE CAMP05 International Workshop on Computer Architecture for Machine Perception, [9] Eri Prasetyo Wibowo, Nur Huda, Desain Skematik, Layout, dan Simulasi dengan Menggunakan Perangkat Lunak Mentor Graphics. Depok: Gunadarma University, March 2007.

7 Advanced Technologies in Nano Materials and Electric Devices / A 8-Bit DAC Design in AMS 0.35 μm CMOS Process for High-Speed Communication Systems /