A TDC based BIST Scheme for Operational Amplifier Jun Yuan a and Wei Wang b

Transcription

1 Applied Mechanics and Materials Submitted: ISSN: , Vols , pp Accepted: doi: / Online: Trans Tech Publications, Switzerland A TDC based BIST Scheme for Operational Amplifier Jun Yuan a and Wei Wang b 1 School of Electroning Engineering/Chongqing International Semiconductor School, Chongqing University of Posts and Telecommunications, Nan an District, Chongqing, China a yuanjun@cqupt.edu.cn, b wangwei@ cqupt.edu.cn Keywords: built-in Self-Test, inverter, time-to-digital converter, operational amplifier Abstract. This paper presents a time-to-digital converter (TDC) based built-in self-test (BIST) scheme for operational amplifier (Op Amp). The propagation delay exiting in the transient response of the Op Amp is monitored by the inverter based TDC, and converted into a digital code based on the referenced delay interval of the inverter used in the TDC, as a result, the digital code is finally employed to determine the test rsults. The circuit-level simualtion results of the proposed BIST syetem for a two-stage Op Amp are presented to demonstrated the feasility of the proposed BIST scheme with high fault coverage. Introduction The rapid development of IC fabrication technology and the advance of SoC design technology have made it possible to integrate digital and analog components on a single chip. These mixed-signal circuits are widely used in various devices. Compared to logic codes of digital circuits, the performance parameters of the analog circuits are hard to be measured due to the small fluctuation range. The smaller analog blocks make the complex mixed-signal circuits more sensitive to fabrication variations and tolerance accumulations [1], and the cost to produce mixed-signal devices is being dominated by their analog test costs [2]. Therefore, the test of analog blocks in mixed-signal circuits has attracted lots of research attentions. Additionally, the accessibility and observability of the analog block in the mixed-signal circuits are limited by the high integration, so as an effective solution to the traditional off-chip test, BIST techniques, implementing both stimulus generator and response analyzer entirely on-chip, are widely applied in mixed-signal testing. Conventionally, performance parameters were measured on-chip to test analog blocks, but this specification-driven BIST techniques result in high-test costs due to complex testing circuits and test time. Therefore, another structural test technique, fault-based BIST was proposed to detect the possible physical defects caused through the IC production. As the basic parts of analog and mixed-signal circuits, Op Amps have attracted widely research attention, so a large number of fault-based BIST schemes for Op Amp have been proposed. The transient response analysis based test techniques are the most feasible for BIST technique. In [3], the Op Amp under test was converted into a voltage follower, and the transient response was analyzed in order to measure the overshoot and slew rate deviation with respect to the fault-free response. However, the parameters of overshoot and slew rate vary among different Op Amps with different architectures, the designed system must be modified to test other Op Amps, even in the same chip. Therefore, the stable (desired) output value (SOV) checking [4] based BIST was presented, and it can test all the Op Amps in a complex analog and mixed-signal system using only one fixed BIST circuit. Due to the feedback network in the transient test, some slight performance parameters deviations are still hard to be monitored, so another feasible two-step BIST technique [5] for Op Amp was proposed to improve the fault coverage, specifically for the compensation circuit. With the injected test current to the compensation circuit, the fault coverage can be greatly improved, but the designed response analyzer caused high area cost, and the test processing is also complicated. Therefore, a new modified transient response based BIST for Op Amp is proposed, the slew rate of the Op Amp under test is measured by the inverter based TDC, and converted to a digital code for final test result determination. In addition, the nanosecond level delay of the CMOS inverter is All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-05/03/16,06:53:30)

2 3584 Machine Tool Technology, Mechatronics and Information Engineering employed as interval reference, so the time interval for slew rate can be precisely measured and the fault coverage can be dramatically improved. Test Strategy and Technique Inverter based TDC. ADC convert voltage amplitude to digital code and TDC is used to convert time interval to digital code. The traditional implementation approach to time-to-digital conversion is first to convert the time interval into a voltage, and then this voltage is digitized by ADC. With IC technology scaling, analog performance parameters like output resistance or intrinsic gain are degraded while digital circuits become faster, smaller, and less power hungry. Therefore, digital circuits can add-on help to reduce analog power or improve robustness and reliability [6]. As a result, the digital TDCs were proposed, the digital counter was designed to count the reference clocks in the time interval and the counting result is the digital code. To further improve the measurement resolution, among a digital delay-line the delay of buffer or inverter was employed to replace the clock reference. In this paper, inverter is employed as delay element, the inverter based TDC implementation is illustrated in Fig.1. Fig.1 Inverter based TDC. The delay of DE1 is designed to T d, the inverter based TDC shown in Fig.1 can convert time interval from start to stop signal to an 8-bit digital code with the time range from 0 to 8T d. The time interval range can be enlarged by lengthening the delay-line, the resolution also can be improved by modifying the transistor sizes of the inverter in each delay element. TDC based Slew Rate Measuring. Many parameters like slew rate (SR), setting time, and phase margin of an Op Amp can be captured and calculated from the transient response. The transient response finally rise or fall to a stable voltage value with a little propagation delay according to the input step, which skipped from an initial voltage to another stable voltage. If the input step magnitude is sufficiently large, the Op Amp will slew by virtue of not having enough current to charge or discharge the compensating and/or load capacitances. The slew rate is determined from the slop of the output waveform during the rise or fall of the output [7]. The output waveform is the so-called transient response. Under voltage follower configuration shown in Fig.2, a step signal is send to V i skipping from V 1 to V 2, the output V o rises from V 1 to the final stable value of V 2 through the propagation region according to the step input. To calculate the value SR, two nodes N 1 and N 2 are selected on the output V o, and the rising slop (also SR) can be computed using the formula of (SR=V d /T i, where V d is the voltage slewing rage from node N 1 to N 2, and T i is the required time interval in which V o changes from node N 1 to N 2.). To test the Op Amp, the reference SR is obtained by simulating the fault-free Op Amp, the value of SR is measured and calculated to compare with the reference value during the field test process. If the measured SR value is without of the acceptable range, the Op Amp under test is determined as a faulty device. However, the aim to calculate and measure SR is to test the Op Amp, SR can be replaced by other prameter for much easier test buliding. In SR=V d /T i, if value of V d is a fixed, only slew time T i is need to demonstrate the test result. As a result, the left work is to measure the delay interval T i according to a fixed V d, and the interval measurement can be easily achieved by TDC to convert T i to a digital code.

3 Applied Mechanics and Materials Vols Fig.2 shows the test result determination process. Firstly, a step input is generated and send to the Op Amp under test through V i, then the output V o would rise from V N1 to V N2, which are set to fix the voltage difference V d in advance. In the second, when V o passed by V N1 at node N 1, a digital start signal is send to the TDC through the start, then this signal flows through each delay element (DE1~DE8) in the delay-line. The digital stop signal isn t send to all flip-flops in the TDC to latch the output of each delay element until the voltage magnitude of V o reaches at V N2 at node N 2. Finally, the output "Q 1 ~Q 8 " is the test result determination criterion. In this paper, with well setting of nodes (N 1 and N 2 ) and the delay of each DE in advance, the rising edge of the start signal would not pass through DE8 after T i for a fault-free Op Amp, T i and T DE should comply with 7T DE <T i <8T DE, that means the fault-free output code is " ". If any output code is not " ", the Op Amp under test is faulty. v i VDD OpAmp v o GND v i v 2 v 1 T i v o v 1 v d v 2 start stop Q 1 ~Q 8 `0` `0` `0` N 1 N 2 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 Fig.2 TDC based Op Amp test strategy by measuring slew rate. `1` `1` `1` Test System Implement To implement the test strategy mentioned above, beside the inverter based TDC shown in Fig.1, step input, start signal and stop signal need be generated, and the complete test system is shown in Fig.3. The test process starts when test start signal V ts skips from logic high to low. When V ts is logic high, the step signal generator including transistor M1, M2 and R, outputs V 1 and is send V i, and then V ts changes to logic low which turn on transistor M2 and force V i to another voltage V 2. Therefore, by controlling the test start signal V ts, M1, M2, and R can generate a step signal. Meanwhile, the switch S i and S o are turned on, so V o will be send to two amplifiers amp1 and amp2, and each amplifier is composed of two same inverters. Different designed transistor sizes between inv1 and inv2, contribute different gains of amp1 and amp2. The outputs of amp1and amp2 would change from logic low to logic high at different moments during the voltage rising from V 1 to V 2. The time interval between outputs switching moments of amp1and amp2 was designed to be T i, so the output V o passes through amp1 and amp2 and generate two controlling the signals start and stop, which control the inverter based TDC to convert T i to the digital code "Q 1 ~Q 8 ". The test controller monitors the output of TDC and determines the test results. Fig.3 The proposed TDC based BIST system for Op Amp.

4 3586 Machine Tool Technology, Mechatronics and Information Engineering Simulation Results Fault models are introduced as equivalent circuits, which are injected into circuit under test to reflect the behavior of realistic physical failures cased in production process. In this paper, 6 fault models were utilized for each transistor to evaluate the proposed test system. Shorts were modeled by connecting a small resistor of 100 Ω between each pair of terminals, including gate-drain short (GDS), gate-source short (GSS), drain-source short (DSS) and resistor short (RS). Opens were modeled by inserting a parallel combination of a large resistor of 100 MΩ and a small capacitor of 10 ff in series into each terminal, including drain open (DO), source open (SO) and resistor open (RO). Particularly, gate open (GO) was modeled by means of grounded parallel combination of resistor and capacitor for simulating real behavior of GO [8]. To evaluate the proposed BIST scheme, a two-stage Op Amp shown in Fig. 4, was considered as test vehicle, and transistor sizes are summarized in Table 1. Fig.4 The circuit configuration of the two-stage Op Amp under test. Table 1 Summary of elements parameters of the two-stage Op Amps. Op Amp Elements Size (unit) Elements Size (unit) Two-stage M0, M5 5.4/0.4 W/L [µm] M1, M2 12/0.4 W/L [µm] Op Amp M3, M4 10.2/0.4 W/L [µm] M6 34/0.4 W/L [µm] Shown in M7 9/0.4 W/L [µm] M8 0.8/0.4 W/L [µm] Fig. 4 R C 18 [kω] C C 1 [pf] C L 10 [pf] By setting M1, M2 and R shown in Fig.3 as 2.8/0.4 µm (W/L), 1.8/0.4 µm (W/L), and 3.29 kω, respectively, the step signal generator can generate the step signal skipping from V (value of V 1 ) to V (value of V 2 ) by controlling test start signal V ts. The sizes of pmos and nmos in amp1 were set as 0.4/0.18 µm (W/L) and 2/0.18 µm (W/L), respectively. The sizes of pmos and nmos in amp1 were set as 5/0.18 µm (W/L) and 0.4/0.18 µm (W/L), respectively. Additionally, to comply with 7T DE <T i <8T DE, the transistor sizes in DE1~DE8 of the delay-line shown in Fig.1 were set as 2/1 µm (W/L), other transistors were set to 0.4/0.18 µm (W/L). Using TSMC 0.18 µm technology, the whole system was simulated by LTspice and the fault-free responses are illustrated in Fig.5. The outputs of DE1~DE8 are labeled as V de1 ~V de8, the fault-free "Q 1 ~Q 8 " is " ". Under test mode, if the " Q 1 ~Q 8 "is not " ", the inserted fault can be detected and Op Amp under test is faulty. To verify the proposed TDC based test system, 54 faults as mentioned before were inserted in the Op Amp shown in Fig.4, only DO of M11 was not detected and the fault coverage is more than 98%. In addition, more than 0.3 pf variation of C c and more than 0.9 kω variation of R c were detected. Summary In order to improve the Op Amp test precision, this paper has proposed a BIST scheme, in which the delay of the CMOS inverter was employed as reference interval to measure the time interval for test

5 Applied Mechanics and Materials Vols results determination based on inverter based TDC. Due to the delay of CMOS inverter is under nanosecond level, the proposed test system could provide precise time interval measurement and achieve high fault coverage. Additionally, thanks to the inverter based fully digital TDC, the proposed BIST scheme can be easily integrated with other analog and mixed signal circuits. Using 0.18-µm TSMC technology, the 8-bit TDC based BIST system was implemented for a two-stage Op Amp and the fault simulation has shown the proposed scheme could be an alternative and effective test approach for Op Amp with high fault coverage. The proposed BIST scheme can also be applied to test other amplifiers or analog circuits for time interval measurement. Fig.5 Fault-free output of the proposed TDC based BIST system for Op Amp. Acknowledgements This work was financially supported by the Youth Science Foundation (A ) and the PhD Start-up Fund (A ) of Chongqing University of Posts and Telecommunications, the Chongqing Municipal Science and Technology Commission Foundation and Advanced Research Project (cstc2013jcyja40006) and Chongqing City Board of Education Science and Technology Research Projects (KJ130530). References [1] P. Kabisatpathy, A. Barua and S. Sinha, Fault Diagnosis of Analog Integrated Circuits, Springer (2011). [2] G.W. Roherts, Chapter 6.2 DFT techniques for Mixed-signal Integrated Circuits, 97.pdf [3] J. Font-Tossello, etc., A Digital BIST for Opamps Embedded in Mixed-Signal Circuits by Analysing the Transient Response, IEEE Int. Caracas Conf. On Devices, Circuits and Systems, Aruba, pp , [4] J. Yuan and M. Tachibana, A BIST Scheme for Operational Amplifier by Checking the Stable Output of Transient Response,20th European Conference on Circuit Theory and Design, Linkoping, Sweden, Aug , [5] J. Yuan and M. Tachibana, A Two-Step BIST Scheme for Operational Amplifier, Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2012), Beppu, Japan, Mar [6] S. Henzler, Time-to-Digital Converter, Springer (2010). [7] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 2nd ed., vol. 2. Oxford: New York, [8] U. Kac and F. Novak, Oscillation Test Scheme of SC Biquad Filters based on Internal Reconfiguration, J. Electron Test, Vol.23, No.6, pp , 2007.

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