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1 894 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 56, NO. 5, MAY 2009 A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration Hee-Cheol Choi, Young-Ju Kim, Student Member, IEEE, Gil-Cho Ahn, Member, IEEE, and Seung-Hoon Lee, Member, IEEE Abstract This paper describes a 12-b 120-MS/s dual-channel pipeline analog-to-digital converter (ADC) for high-speed video signal processing. A simple digital midcode calibration technique is proposed to eliminate an offset mismatch between two channels. The proposed sample-and-hold-amplifier-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a m CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1 db and a peak spurious-free dynamic range of 74.7 db for input frequencies up to 60 MHz at 120 MS/s. The measured differential and integral nonlinearities are within 0 30 LSB and 0 95 LSB, respectively. The ADC occupies an active die area of 0 56 mm 2 and consumes 51.6 mw at a 1.2 V power supply. Index Terms Analog-to-digital converter (ADC), CMOS analog integrated circuit, comparator offset, dual channel, input sampling network, low power, midcode calibration, sample-and-hold amplifier (SHA) free, switched operational amplifier (op-amp). I. INTRODUCTION T HE demand for high-resolution and high-speed analog-to-digital converters (ADCs) has been continuously increased for various applications such as CMOS image sensors, communications, and video analog front-end applications. In particular, some state-of-the-art digital TVs and cable applications require ADCs with a resolution of up to 12 b and a sampling rate exceeding 110 MS/s [1] [4]. Moreover, the required specifications concerning data conversion speed and resolution are becoming more and more strict in order to obtain higher display resolution and better image quality. In video applications, most signal formats are based on a multichannel configuration. For example, component video signal and RGB PC outputs use three channels. Thus, multiple ADCs are essential in a system-on-a-chip (SoC) to process these video signals, and the system cost can be reduced depending on the shrinking die size of the ADCs. On the other hand, the power consumption of the ADCs is no longer negligible in those SoC applications. The total power consumption of the chip also affects both the reliability and the cost of the employed package. As a result, low power consumption and compact size together with high resolution and high sampling rate have Manuscript received September 23, 2008; revised December 23, First published February 13, 2009; current version published May 20, This work was supported by the System IC 2010 Project of Korea Ministry of Knowledge Economy and the IDEC of KAIST, Korea. This paper was recommended by Guest Editor A. Chan Carusone. The authors are with the Department of Electronic Engineering, Sogang University, Seoul , Korea ( hoonlee@sogang.ac.kr). Digital Object Identifier /TCSI Fig. 1. Block diagram of a time-interleaved ADC architecture. been key design issues for the development of a single-chip integrated system to process high-quality video signals. Usually, the power consumption and chip size of conventional ADCs tend to be linearly proportional to the conversion speed within a specific sampling frequency range. Similarly, the power consumption of the ADCs increases with a required resolution at a given sampling rate. Sometimes, for example, at a sampling rate exceeding hundreds of megahertz, the ADCs cannot increase the conversion speed even though more power is invested. A couple of time-interleaved ADCs address such performance-limited issues as conversion speed, resolution, and power consumption [5], [6]. The time-interleaved ADC architecture shown in Fig. 1 is an example of one of the most efficient ways to implement a high sampling rate with moderate power consumption. The time-interleaved ADC consists of ADCs in parallel, a demultiplexer at the analog input, and a multiplexer (MUX) at the digital output. Each ADC channel operates at a sampling rate of [fs/m]. The transfer function of the ADC in each channel needs to be identical while the clock skew is required to be matched for a highly linear signal sampling operation. The challenges in the design of high-resolution, time-interleaved ADCs come with a couple of constraints associated with static and dynamic errors. Static errors are caused by offset and gain mismatches between channels, while dynamic errors originate from mismatches at a sampling instant. Static errors limit a signal-to-noise ratio (SNR), independently of input frequencies and sampling rates. On the other hand, dynamic errors result in an input-frequency-dependent SNR degradation. Typically, dynamic errors with a low-frequency input signal are negligibly small in switched capacitor applications. However, static errors always result in destructive problems. Much effort has been devoted to overcome the static mismatches. Channel offsets have been cancelled out by well-known analog domain circuit techniques such as auto-zero offset cancellation, correlated double sampling [7], and chopper stabilization [8] /$ IEEE

2 CHOI et al.: SHA-FREE DUAL-CHANNEL NYQUIST ADC BASED ON MIDCDE CALIBRATION 895 However, those techniques tend to require wideband analog circuits, and they generate some critical noise issues as well as increase the total power consumption, particularly in various high-speed video signal applications. Another efficient way to eliminate static mismatches is to apply a calibration technique in the digital domain [6], [9] [11]. The calibration-related extra circuits increase the complexity, area, and power of the integrated ADCs. However, the overhead of these circuits can be scaled down significantly with the development of advanced CMOS technologies and various calibration algorithms. This study proposes a low-power, dual-channel Nyquist pipeline ADC, which can operate at a sampling rate of 120 MS/s with a 1.2-V supply voltage based on a m CMOS process. The main focus of this study is on a static error reduction due to offset and gain mismatches of the time-interleaved ADC, rather than a dynamic error reduction. The dual-channel ADC architecture with digital channel offset cancellation is described in Section II. Low-power circuit design techniques for a gain mismatch reduction without calibration are discussed in Section III. The implementation and measurement results of the prototype ADC are summarized in Section IV. Finally, conclusions are drawn in Section V. Fig. 2. Block diagram of the proposed dual-channel ADC. II. ADC ARCHITECTURE AND CALIBRATION A. ADC Architecture One of the most popular schemes to increase a resolution of pipelined ADCs is a calibration technique regardless of singlechannel ADCs or time-interleaved multichannel ADCs. The calibration technique is classified into foreground and background calibration, depending on the time when calibration is to be performed. Conventional foreground calibration techniques suffer from a disadvantage that ADCs need to hold operation and be calibrated repeatedly in the middle of operation due to time-dependent temperature and voltage variations. For high-resolution ADCs, it takes a long time to be calibrated, and some foreground calibration cannot be employed in a specific application. To overcome this shortcoming, background calibration techniques without an extra calibration phase have been proposed [12], [13]. However, the background calibration techniques also need a long initial calibration time to obtain a required accurate resolution while calibration logic requires a large area and power consumption. This paper proposes a foreground midcode calibration technique with a short calibration time and a small number of digital logic gates for a small chip size and low power consumption. The proposed dual-channel 12-b 120-MS/s ADC is shown in Fig. 2. It consists of an analog demultiplexer at the input, two ADCs in parallel, a midcode calibration circuit, and a digital multiplexer at the output. Each ADC channel operates at a sampling rate of 60 MS/s with externally controlled opposite phase clocks, CLK and CLKB. The digital output multiplexer and midcode calibration logic circuits are implemented off chip. The proposed digital midcode calibration technique combined with some circuit designs efficiently eliminates channel offsets and gain mismatches between two channels with only very limited digital circuitry in the integrated time-interleaved Fig. 3. Single-channel ADC architecture of Fig. 2. ADCs [14]. The calibration time and complexity based on the proposed scheme are almost independent of the resolution and conversion speed of the ADC. The offset in each single-channel ADC is also reduced by this technique. The single-channel 12-b 60-MS/s ADC, as shown in Fig. 2, is detailed in Fig. 3. The ADC consists of five multiplying digital-to-analog converters (MDACs), six flash ADCs (FLASHs), an on-chip current reference, and other supplementary circuits. A gain mismatch between channels is minimized by employing a sampling-and-hold amplifier (SHA)-free architecture together with a resistor-free FLASH scheme. B. Calibration The proposed dual-channel ADC, as shown in Fig. 2, employs off-chip midcode calibration logic, marked as MC CAL, and two clock phases, CLK and CLKB. Calibration starts with a control signal CAL switched to high at the input. During this calibration period, the positive and negative analog inputs of each channel are tied together, and external inputs are disconnected from the ADC. The offset error of each channel ADC is measured separately by averaging the digital outputs 16 times. Each averaged and rounded off digital code is subtracted from the ideal midcode, 2048, and the results are stored in memory. This foreground calibration procedure takes only 22 clock cycles, including the initial meaningless four clock cycles for the pipeline delay. During normal conversion, each measured and stored offset is subtracted from the raw digital outputs of each channel ADC, and the calibrated digital output from each channel is time-interleaved by the digital MUX block at the output. Off-chip digital calibration logic for midcode calibration can be implemented with a simple structure, which

3 896 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 56, NO. 5, MAY 2009 Fig. 4. Functional description of a midcode digital calibration (f =f =16) (a) before and (b) after calibration. corrects only one code. It occupies less than 500 logic gates for a calibration range of 128 codes which eliminate a channel offset voltage of mv level. The digital midcode calibration concept is briefly described in Fig. 4. Fig. 4(a) shows the measured patterns of the prototype ADC before calibration. The output of each channel is shifted by and, respectively, and shows a dc component in the fast Fourier transform (FFT) spectrum. With the time-interleaving technique, the dc component is modulated at the zero frequency, and a spurious tone appears at [fs/2]. A gain mismatch between channels results in a spurious component at [fs/2-fin] in the FFT plot of the time-interleaved outputs, but it does not show up in each single-channel ADC. It significantly degrades the SNR performance of the prototype ADC, and the effective resolution is limited up to around 8 b or less. A timing mismatch can also cause a spurious tone at [fs/2-fin] in the same way as a spurious component due to a gain mismatch. In this work, since this tone to be generated by a timing mismatch is minimized by carefully controlled external clocks, the tone at [fs/2-fin] is composed of a spurious component resulting from a gain mismatch. The normalized minimum magnitude of each noise tone can be summarized as [15]. The spurious tone due to a gain error of in (2) comes primarily from the average gain difference between the two ADC channels. The proposed midcode calibration removes offsets such as and. After calibration, as observed in Fig. 4(b), the dc component of each channel output and the spurious tone at [fs/2] of the time-interleaved outputs are simultaneously reduced in the FFT plot. (1) (2) The proposed midcode calibration technique needs the linearly increased number of digital logic gates depending on the interleaved number of ADC channels used for high speed operation. The fact that the required calibration time remains constant even with the increased number of channels makes the proposed foreground calibration technique adequate for many applications. III. ADC CIRCUIT DESIGN A high unity-gain frequency required for analog circuits such as operational amplifiers (op-amps) can be obtained using thin gate oxide and short-channel active devices with a reduced parasitic capacitance and a smaller device dimension resulting from the downscaling of CMOS technology. This offers low-power consumption as well as high-speed operation. However, these merits also come with demerits, which are not critical in the conventional design but should be overcome by other advanced circuit techniques in the new era of deep-submicrometer technology [16]. First of all, the variation of switch on-resistance dependent on signal levels significantly limits the linearity of sampled inputs in low-voltage applications, and restricts the accuracy of circuits in high-speed operations. Second, noise performance is considerably degraded with a reduced voltage range. In other words, a reduced signal swing decreases the SNR due to the noise power, independent of the power supply. Finally, offset voltages are increased due to the short channel length and small device dimension. Offset reduction requires additional circuit design schemes such as calibration or offset cancellation using an auto-zero function. In this study, a gate-bootstrapping technique is employed to improve the high-speed input sampling performance [17] while an op-amp with a high signal swing is used to address the noise problem. As discussed in Section II, the proposed calibration technique eliminates channel offsets. As for the conventional pipeline ADCs, primary gain errors come from the nonlinear op-amp in the input SHA as well as

4 CHOI et al.: SHA-FREE DUAL-CHANNEL NYQUIST ADC BASED ON MIDCDE CALIBRATION 897 Fig. 5. Simplified input sampling network based on MDAC1 and FLASH1. the unmatched top and bottom reference voltages supplied to each functional circuit block. This study proposes an SHA-free input sampling network to eliminate the major channel-gain mismatch error resulting from a mismatched SHA gain. The gain mismatch can occur due to a reference voltage difference between channels. A resistor-free FLASH ADC architecture is proposed to remove the non-linear reference voltage mismatch effect due to the parasitic resistance of interconnection metal lines. An op-amp gain error of the MDAC1 may cause an other gain mismatch between channels as well as a linearity error of a single channel ADC. However, the error can be maintained negligibly small if each single-channel ADC is designed efficiently to suppress the linearity error due to the first stage MDAC to less than 1 LSB, which is very common and essential for a single-channel ADC design. The circuit design techniques to reduce a gain error without calibration, while maintaining a low power dissipation, are proposed and discussed in the following subsections. A. Input Sampling Network In the proposed SHA free architecture, as shown in Fig. 5, analog inputs are sampled directly at the MDAC1 and FLASH1. When a mismatch occurs between the input sampling time of the capacitor array in the MDAC1 and that of the comparator array in the FLASH1, the maximum allowable input frequency for no-missing code performance is restricted. The input sampling network proposed in Fig. 5 allows a precisely matched sampling time for the MDAC1 and FLASH1 to obtain a high-frequency input sampling even without an SHA. The sampling time mismatch is minimized by synchronizing the sampling time of the switches connected to the bottom plate of each capacitor in the MDAC1 and FLASH1 employing a bootstrapped clock, thus making sampled inputs maintain a good linearity. A sampling time error between the MDAC1 and FLASH1 commonly leads to missing codes. Comparator offsets exceeding the decision-error correction range of the FLASH1 generate the same kind of missing codes. The maximum allowable input frequency for no-missing code is derived as follows: (3) (4) (5) Fig. 6. Simulated conditions of input frequency, sampling time mismatch, and comparator offsets for no-missing code based (a) on MDAC1 with no offset and (b) on MDAC1 with an offset voltage of 15 mv. In (5), is the sampling time mismatch between the MDAC1 and FLASH1. The is the tolerable offset voltage in the ADC and is calculated as follows: In (6), is the maximum allowable offset voltage with no sampling time mismatch. In the proposed SHA-free ADC architecture, the value of needs to be 62.5 mv to guarantee no-missing code. The and are the offset voltages of the MDAC1 and FLASH1, respectively. As shown in (5) and (6), a maximum achievable input sampling frequency is limited by the offset errors of the MDAC1 and FLASH1 as well as the timing mismatches between the MDAC1 and FLASH1. Thus, a maximum allowable input frequency with an MDAC1 offset voltage of and a FLASH1 offset voltage of is calculated as follows: mv (7) In Fig. 6, the required conditions of input frequency, timing mismatch, and offsets of the MDAC1 and FLASH1 are described to achieve no-missing code with a V input signal at a 12-b resolution. As shown in Fig. 6(a), input frequencies for no-missing code are corelated and analyzed with timing mismatch errors and FLASH1 offset voltages of 0 30 mv when the MDAC1 has no offset error. For example, the timing mismatch of the MDAC1 and FLASH1 should be limited to less than 0.33 ns in order to process a high-frequency input signal of 60 MHz, even if the MDAC1 and FLASH1 are ideal without any offset voltages. On the other hand, Fig. 6(b) shows the input frequencies related to tolerable sampling time mismatches and comparator offsets with a given MDAC1 offset of 15 mv. The simulated results of Fig. 6(b) show that the sampling time mismatch should be less than 0.09 ns with offset voltage mismatches of 15 and 30 mv in the MDAC1 and FLASH1, respectively, in order to properly handle a 60-MHz Nyquist input signal in the proposed 12-b ADC. B. Resistor-Free Comparator The proposed ADC is composed of six pipeline stages, and each stage is based on a 2.5-b/stage midrise coding technique, as illustrated in Fig. 7. The small triangles in Fig. 7 represent comparators. Three comparators between DREF and -DREF are (6)

5 898 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 56, NO. 5, MAY 2009 Fig. 7. Coding technique of the proposed ADC. Fig. 9. Two-stage switched op-amp for MDAC1. Fig. 8. FLASH architecture. (a) Capacitor-divided latched comparator. (b) Proposed 2.5-b FLASH scheme. used for normal conversion, while the top and bottom comparators from stage 2 to stage 6 are needed for error correction. Each FLASH is based on a capacitor-divided (C-DIV) comparator instead of a conventional resistor ladder-based comparator, as shown in Fig. 8(a). The schematic of the proposed C-DIV based FLASH circuit is illustrated in Fig. 8(b). With the proposed latched comparator, all the FLASHs are free from having a resistor divider, which can cause a gain error in the ADC due to a voltage drop of reference voltages through interconnection line currents. Each input node in the proposed comparator of Fig. 8(a) and (b) employs two separate capacitors, but the capacitors are connected only to the top and bottom reference voltages, and, selectively. All the FLASHs consist of the same C-DIV type comparators, and the bootstrapped clocks, and, are applied only to the first FLASH in order to deal with a sampling time mismatch. C. Two-Stage Switched Op-Amp As shown in Fig. 9, the MDAC1 employs a two-stage op-amp to achieve a high signal swing with the required high dc gain. Since op-amps are the most power-hungry analog circuits in the pipeline ADC, a cascoded compensation technique [18] and switched op-amp techniques [19] are adopted to minimize the power dissipation of the op-amps. During the sampling phase, transistors M3, M4, and M7 operating as switches are turned off. At the same time, both differential outputs, and, are set to a common-mode voltage of VCOM by transistors M5 and M6. The gate of M9 is connected to VB5 through M8 to achieve a fast settling of each node in the next amplifying phase while maintaining the power off status. Right before the amplifying phase, M7 is turned on first, and M3 and M4 are turned on to amplify input signals at the beginning of the amplifying phase. This slight timing difference between M7 and M3 M4 is needed to reduce the power consumption of the op-amp without degrading the settling time. It is noted that the dynamic common-mode feedback (CMFB) circuit proposed in the second stage op-amp consists of only two capacitors and three switches, as shown in the shadowed area of Fig. 9. The proposed CMFB circuit requires half the components that the conventional switched-capacitor based CMFB circuit [20] does. The CMFB circuit reduces a chip size and power consumption by lowering the output loading capacitance. The total power consumption and chip area of the ADC are reduced by approximately 30%, compared to conventional ADCs with a similar pipeline architecture, based on the proposed switched op-amp and the simplified CMFB circuit. IV. ADC IMPLEMETATION AND MEASUREMENTS The prototype ADC is fabricated in a m CMOS process. Both of the dual channels are symmetrically laid out as illustrated in Fig. 10. Each individual ADC independently integrates all of the functional circuit blocks and does not share any circuit blocks to avoid any potential crosstalk noise between each channel. Dummy capacitors are laid out only in the capacitor array of the MDAC1 to obtain good capacitor matching accuracy, which is very critical to maintain 12-b-level ADC linearity. The reduced number of dummy capacitors and the resistor-free FLASHs minimize the area of passive components occupying a relatively large portion of the entire

6 CHOI et al.: SHA-FREE DUAL-CHANNEL NYQUIST ADC BASED ON MIDCDE CALIBRATION 899 Fig. 13. Measured FFT spectrums of each ADC channel. (fck = 10 MHz; n = 4:5 MHz). (a) A Channel. (b) B Channel. Fig. 10. Die micrograph of the proposed dual-channel ADC. Fig. 14. Measured FFT spectrums of the proposed dual-channel ADC (fck = MHz; n = 4:5 MHz). (a) Before calibration. (b) After calibration. Fig. 11. Measured DNL and INL of each ADC channel. (a) A Channel. (b) B Channel. Fig. 12. Measured DNL and INL of the proposed dual-channel ADC (a) before calibration and (b) after calibration. ADC chip area. The active die area of the dual-channel ADC, excluding off-chip calibration logic, is mm. Figs. 11 and 12 illustrate the measured static linearity performance of two separate ADC channels and the dual-channel time-interleaved ADC, respectively. The proposed dual-channel ADC shows better linearity than each separate single-channel ADC, since the random linearity errors of each single-channel ADC are also averaged out. The proposed offset calibration does not move toward any significant improvement of the linearity, as shown in Fig. 12. The FFT spectrums of two single-channel ADCs and the dual-channel ADC are plotted in Figs. 13 and 14, respectively. The plots of Fig. 13 are measured with an 8192-point FFT, and the plots of Fig. 14 are measured with a point FFT. The input signal frequency is 4.5 MHz, while the sampling rate of each single channel is 10 MS/s to achieve a 20-MS/s sampling rate in the overall ADC. The spurious components of the dotted circle at [fs/2-fin] in the left-hand side of Fig. 14(a) and (b) are caused by a gain mismatch between channels in the time-interleaved ADC. The value of 84.5 dbc representing a gain mismatch is negligibly small at a resolution of 12 b and is almost independent of calibration. On the other hand, the harmonic component at [fs/2] indicating an offset mismatch is 49.8 dbc before calibration, which limits the spurious-free dynamic range (SFDR). The measured channel offset of the prototype ADC corresponds to 13 LSBs at 12 b. The offset spurious tone is improved to 80.9 dbc from 49.8 dbc after the proposed midcode calibration. The proposed midcode calibration reduces the dc component as well as the harmonic component at [fs/2] caused by an offset mismatch. After calibration, as observed in Fig. 14, the dc component of the time-interleaved outputs is reduced to 70.2 dbc from 56.4 dbc. The signal-to-noise-and-distortion ratio (SNDR) and SFDR versus sampling frequencies for a 4.5-MHz input are plotted in

7 900 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 56, NO. 5, MAY 2009 TABLE I PERFORMANCE SUMMARY OF PROTOTYPE ADC Fig. 15. Measured SNDR and SFDR. rate exceeding 50 MS/s, where the FOM is defined as follows: (8) Fig. 16. Measured FFT spectrums with Nyquist input (fs =120MS=s, n = 59:9 MHz). Fig. 17. FOM of recently reported 12-b ADCs with a sampling rate exceeding 50 MS/s. Fig. 15. The SNDR and SFDR maintain a reading of better than 60 and 70 db up to a sampling rate of 120 MS/s, respectively. The dual-channel prototype ADC consumes 51.6 mw at a nominal condition of 120 MS/s and 1.2 V. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the calibrated dual-channel ADC are within LSB and LSB, respectively. The measured SNDR and SFDR are 63.6 and 81.0 db, respectively, with an input frequency of 4.5 MHz and a sampling rate of 20 MS/s. At a sampling rate of 120 MS/s, the measured SNDR and SFDR are 61.1 and 74.7 dbc, respectively, for a 59.9-MHz input frequency as shown in Fig. 16. It is measured with a point FFT. Fig. 17 illustrates a figure of merit (FOM) versus sampling rate of recently reported 12-b CMOS ADCs with a sampling The FOM of the proposed ADC is 0.46 pj/conversion-step. The proposed ADC performance is summarized in Table I. Off-chip digital calibration logic needs a logic gate count of 500 for a calibration range of 128 codes, which requires a small additional chip area less than 0.01 mm and a power consumption of 1 mw. V. CONCLUSION This study proposes a 12-b 120-MS/s dual-channel ADC based on a midcode calibration scheme, which eliminates an offset mismatch between channels. The ADC employs SHA-free as well as resistor-free architectures simultaneously to achieve both a reduced gain mismatch between channels and a small die area. The implemented 12-b Nyquist-rate m CMOS ADC shows a power consumption of 51.6 mw and an active die area of 0.56 mm at a 120-MHz sampling rate. REFERENCES [1] T. Ito, D. Kurose, T. Ueno, T. Yamaji, and T. Itakura, 55 mw 1.2 V 12 bit 100-MSPS pipeline ADCs for wireless receivers, in Proc. Eur. Solid-State Circuits Conf., Sep. 2006, pp [2] C. Michalski, A 12 b 105 Msample/s, 850 mw analog to digital converter, in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2000, pp [3] T. N. Andersen et al., A cost-efficient high-speed 12-bit pipeline ADC in 0.18-m digital CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 7, pp , Jul [4] S. M. Yoo, T. H. Oh, H. Y. Lee, K. H. Moon, and J. W. Kim, A 3.0 V 12 b 120 Msample/s CMOS pipelined ADC, in Proc. IEEE Int. Symp. Circuits Syst., May 2006, pp [5] W. C. Black, Jr and D. A. Hodges, Time interleaved converter arrays, IEEE J. Solid-State Circuits, vol. SC-15, no. 6, pp , Dec [6] S. M. Jamal, D. Fu, N. C.-J. Chang, P. J. Hurst, and S. H. Lewis, A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration, IEEE J. Solid-State Circuits, vol. 37, no. 12, pp , Dec [7] C. Enz and G. Temes, Circuit techniques for reducing the effects of opamp imperfections: Autozeroing, correlated double sampling and chopper stabilization, Proc. IEEE, no. 11, pp , Nov [8] C. C. Enz and E. A. Vittoz, A CMOS chopper amplifier, IEEE J. Solid-State Circuits, vol. SC-22, no. 3, pp , Jun [9] C. R. Grace, P. J. Hurst, and S. H. Lewis, A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration, IEEE J. Solid- State Circuits, vol. 40, no. 5, pp , May 2005.

8 CHOI et al.: SHA-FREE DUAL-CHANNEL NYQUIST ADC BASED ON MIDCDE CALIBRATION 901 [10] Z. M. Lee, C. Y. Wang, and J. T. Wu, A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration, IEEE J. Solid-State Circuits, vol. 42, no. 10, pp , Oct [11] S. Huang and B. C. Levy, Adaptive blind calibration of timing offset and gain mismatch for two-channel time-interleaved ADCs, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 6, pp , Jun [12] J. Yuan, N. Farhat, and J. Van der Spiegel, Background calibration with piecewise linearized error model for CMOS pipeline A/D converter, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 2, pp , Feb [13] J. L. Fan, C. Y. Wang, and J. T. Wu, A robust and fast digital background calibration technique for pipelined ADCs, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 6, pp , Jun [14] H. C. Choi, Y. J. Kim, S. W. Lee, J. Y. Han, O. B. Kwon, Y. L. Kim, and S. H. Lee, A 52 mw 0:56 mm 1.2 V 12 b 120 MS/s SHA-free dualchannel Nyquist ADC based on midcode calibration, Proc. ISCAS, pp. 9 12, May [15] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, Explicit analysis of channel mismatch effects in time-interleaved ADC systems, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp , Mar [16] S. C. Lee, Y. D. Jeon, and J. Kim, A 10-bit 205-MS/s 1:0 mm 90-nm CMOS pipeline ADC for flat panel display applicxations, IEEE J. Solid-State Circuits, vol. 42, no. 12, pp , Dec [17] A. M. Abo and P. R. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter, IEEE J. Solid-State Circuits, vol. 34, no. 5, pp , May [18] B. Ahuja, An improved frequency compensation technique for CMOS operational amplifiers, IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp , Dec [19] H. C. Choi, J. H. Kim, S. M. Yoo, K. J. Lee, T. H. Oh, M. J. Seo, and J. W. Kim, A 15 mw 0:2 mm 10 b 50 MS/s ADC with wide input range, in ISSCC Dig. Tech. Papers, Feb. 2006, pp [20] R. Castello and P. Gray, A high-performance micropower switchedcapacitor filter, IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp , Dec Hee-Cheol Choi was born in Seoul, Korea. He received the B.S., M.S., and Ph.D. degrees in electronic engineering from Sogang University, Seoul, Korea, in 1994, 1996, and 2009, respectively. From 1996 to 2006, he was a Senior Engineer with Samsung Electronics. He is currently a Senior Engineer with Aptina Korea. His work focuses mainly on sensor chip design, and his current interests are high-resolution low-power CMOS data converters and analog front ends for video signal processing. Young-Ju Kim (S 08) received the B.S. and M.S. degrees in electronic engineering from Sogang University, Seoul, Korea, in 2005 and 2007, where he is currently working toward the Ph.D. degree. His current interests are in the design of high-resolution low-power CMOS data converters and very high-speed mixed-mode integrated systems. Mr. Kim was the recipient of the HumanTech Thesis Contest Silver Award from Samsung Electronics Corporation in Gil-Cho Ahn (M 96) received the B.S. and M.S. degrees in electronic engineering from Sogang University, Seoul, Korea, in 1994 and 1996, respectively, and the Ph.D. degree in electrical engineering from Oregon State University, Corvallis, in From 1996 to 2001, he was a Design Engineer with Samsung Electronics, Kiheung, Korea, working on mixed analog and digital integrated circuits. From 2005 to 2007, he was with Broadcom Corporation, Irvine, CA, working on AFE for digital TV. Currently, he is an Assistant Professor with the Department of Electronic Engineering, Sogang University. His research interests include high-speed, high-resolution data converters and low-voltage, low-power mixed-signal circuits design. Dr. Ahn received the Analog Devices Outstanding Student Designer Award in Seung-Hoon Lee (M 91) received the B.S. and M.S. degrees ) with honors) in electronic engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in From 1990 to 1993, he was with Analog Devices Semiconductor, Wilmington, MA, as a Senior Design Engineer. Since 1993, he has been with the Department of Electronic Engineering, Sogang University, Seoul, Korea, where he is now a Professor. He has been serving as the Chief Editor of the IEEK Journal of Semiconductor Devices, Circuits, and Systems and a TPC member of many international and domestic conferences including the IEEE Symposium on VLSI Circuits. His current interest is in the design and testing of high-resolution high-speed CMOS data converters, CMOS communication circuits, integrated sensors, and mixedmode integrated systems.

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