Design of a 3rd order Delta-Sigma Modulator with a Frequency Detection Circuit

Transcription

1 Design of a 3rd order Delta-Sigma Modulator with a Frequency Detection Circuit Han-Ul Lee 1, Keon Lee 1, Dai Shi 1, Dong-Hun Lee 1, Kwang-Sub Yoon 1, 1 Department of Electronic Engineering, Inha University, South Korea oulmandoo@gmail.com Abstract. This paper proposes a design of a 3rd order delta-sigma modulator with a frequency detection circuit to process both EEG and EMG signals. The power consumption and FOM can be optimized by selecting one of the two integrators (one for EEG and another for EMG), depending on the frequency of input signals. The simulated performance of the proposed modulator shows 98dB SNDR, 16bit ENOB, and 2.4mW of power dissipation with 1.8V of Supply Voltage at 256 KHz of conversion rate and 1 KHz of input frequency. Keywords: Delta sigma, modulator, Frequency Detection, EEG, EMG 1 Introduction Today, due to the development of science and technology, interests for human health is increasing rapidly and bio signals such as electroencephalogram(eeg) and electromyogram(emg) are studied variously [1][2]. It is more increased to utilize multiple bio signals simultaneously rather than to utilize each bio signal separately. Especially, EEG and EMG signals are mainly used at a time to measure and to analyze bio signals [3][4]. Meanwhile, developments of the A/D Converter processing bio signals are in progress in many ways. However, A/D Converter optimized for EEG and EMG signals cannot be used at the same time because of the differences in the frequency band of EEG and EMG signals [5]. According to the trends making the products portable in the medical field, the circuit design techniques for integration and low power are required to process EEG and EMG signals simultaneously. Therefore, this paper places a focus on the design of the delta-sigma modulator to process both EEG and EMG signals. In section 2, the proposed architecture is presented with the operational principle. The simulation results are shown in section 3. The conclusion is drawn in section 4. 17

2 2 Architecture A delta-sigma technique permits us to take a significant advantage from the oversampling approach. This technique has become an attractive solution for low bandwidth and high resolution data converters. Many products use this technique since the noise shaping property results in higher resolution. Moreover, the modulator doesn t need high precision analog components and greatly relaxes anti-aliasing filter requirements as well. Fig. 1. illustrates a conventional delta-sigma A/D Converter system block diagram. A delta-sigma modulator is a feedback system and contains integrator and quantizer. Most of the quantization errors lie outside the signal band and are eliminated by the digital filter. In the last stage, the data are decimated to reduce the sampling frequency to the nyquist frequency, and the result is signal coded in a large number of bits at the nyquist rate. Fig. 1. One Block diagram of the conventional delta-sigma A/D Converter system The proposed third order delta-sigma modulator is composed of an analog-todigital converter, a digital -to- analog converter, and an integrator. High order deltasigma modulators are used to get a better resolution although it increases the number of integrators [6]. In case of composing a high order delta-sigma modulator, the performance of a first integrator is the main factor to determine the performance of the modulator. Therefore, the first integrator is designed to achieve the highest resolution of the modulator [7]. There was a limitation that conventional delta-sigma modulators which were designed for specific bio signal frequency band was unable to obtain a high resolution in case of the different bio frequency band [8]. If the input signal frequency is higher than the target frequency, the integrator in modulator limits the frequency and lowers the performance. On the contrary, the modulator consumes more power than necessary if the input signal frequency is lower than the target frequency. This results in lowering the overall performance of the modulator. In this paper, a frequency detection circuit is employed to the modulator to improve the problem of conventional delta-sigma modulators mentioned previously. Fig. 2. illustrates the block diagram of the proposed delta-sigma modulator. 18

3 Fig. 2. One Block diagram of the proposed delta-sigma modulator The input signal goes through the frequency detection circuit and the output signal of the frequency detection circuit controls selection of the integrator of modulator. If the input signal frequency is greater than the reference frequency, (that is, EMG signal) the output signal of the frequency detection circuit selects the high performance operational amplifier within the first integrator. On the other hand, if the input signal frequency is lower than the reference frequency, (that is, EEG signal) the output signal of the frequency detection circuit drives the low performance operational amplifier within the first integrator. The proposed circuit reduces the power consumption by shutting down the operational amplifier which is not used. Block diagram of the frequency detection circuit is shown in Fig. 3. Fig. 3. Block diagram of the Frequency Detection circuit In the frequency detection circuit, the transistor MN1 is used as a switch to control the current flow which charges and discharges the capacitor C1 according to the input signal, Fin. When the input signal becomes fast, the charging and discharging speed is so fast that the capacitor is charged with small amount of electric charges. On the contrary, when the input signal goes slow, the charging and discharging speed is slow 19

4 enough to charge the capacitor a large amount of electric charges. The voltage across the capacitor C1 is compared with reference voltage and the output signal of comparator determine Vout, the output of the D flip-flop. In other words, if the voltage across C1 is greater than Vref, the output of the comparator becomes high and consequently, it drives Vout to become high. Therefore the high Vout enables the first integrator to select the low performance operational amplifier. Otherwise, the high performance operational amplifier is selected by the output of the D flip-flop. Therefore, the delta-sigma modulator presented in this paper is able to process both EEG and EMG signals and reduce the power consumption. The proposed delta sigma modulator is implemented using a fully differential switched-capacitor technique. A fully differential topology has basically two advantages: 1) a higher immunity to environmental noise and 2) a wider DR. A fully differential folded-cascode opamp with switched-capacitor common-mode feedback (SCCMFB) was employed. The SCCMFB is based on the use of switched capacitors and has an advantage in power reduction, because no static current is consumed to generate the midpoint of the differential swing. The 1bit D/A Converter is implemented using a switch, and the comparator used for the 1bit A/D Converter. The design requirement of the comparator in the modulator is relaxed because the nonidealities of the comparator undergo noise shaping by the loop filter. Therefore, we employed a simple dynamic regenerative comparator. The modulator was designed with the architecture of the 3rd order feedforward delta-sigma modulator. The feedforward architecture becomes suitable for bio signals processing because it tends to be smaller and less power than feedback circuit in low frequency signals [9]. 3 Simulation Results Fig. 3. shows the power spectral density (PSD) of the 3rd order feedforward Delta Sigma modulator at the input signal frequency of 5 KHz. It illustrates the SNDR of 98dB and the ENOB of 16 bit at the sampling frequency of 256 KHz and the bandwidth of 1 KHz. The noise shaping is observed from 20 KHz. The overall power dissipation becomes 2.4mW with the power supply of a 1.8V. 20

5 Fig. 4. Spectrum of 3rd order feedforward Delta-Sigma Modulator 4 Conclusion This paper proposes a design of a 3rd order delta-sigma modulator with a frequency detection circuit. The frequency detection circuit enables the first integrator to select either high performance or low performance operational amplifier, depending on the input frequency. This circuit allows the modulator to optimize the dynamic performance to process both EEG and EMG. The simulated performance of the proposed modulator shows SNDR of 98dB and ENOB of 16bit with the supply voltage of 1.8V, at the conversion rate of 256 KHz and input frequency of 1 KHz. Acknowledgments. This work was supported by the IDEC. This research was supported by the MKE(The Ministry of Knowledge Economy), Korea, under the CITRC(Convergence Information Technology Research Center) support program (NIPA-2012-H ) supervised by the NIPA(National IT Industry Promotion Agency References 1. Ha-Chul Jung; Jin-Hee Moon; Dong-Hyun Baek; Jae-Hee Lee; Yoon-Young Choi; Joung- Sook Hong; Sang-Hoon Lee;, "CNT/PDMS Composite Flexible Dry Electrodesfor Long- Term ECG Monitoring," Biomedical Engineering, IEEE Transactions on, vol.59, no.5, pp , May Chi, Y. M.; Maier, C.; Cauwenberghs, G.;, "Ultra-High Input Impedance, Low Noise Integrated Amplifier for Noncontact Biopotential Sensing," Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol.1, no.4, pp , Dec

6 3 Qi Yang; Siemionow, V.; Wanxiang Yao; Sahgal, V.; Yue, G.H.;, "Single-Trial EEG-EMG Coherence Analysis Reveals Muscle Fatigue-Related Progressive Alterations in Corticomuscular Coupling," Neural Systems and Rehabilitation Engineering, IEEE Transactions on, vol.18, no.2, pp , April Aliverti, A.; Frigo, C.; Andreoni, G.; Baroni, G.; Bonarini, A.; Cerveri, P.; Crivellini, M.; Dellaca, R.; Ferrigno, G.; Galli, M.; Pedrocchi, A.; Rodano, R.; Santambrogio, G.C.; Tognola, G.; Pedotti, A.;, "Functional Evaluation and Rehabilitation Engineering," Pulse, IEEE, vol.2, no.3, pp.24-34, May-June oes a lino into onteiro a and ar o o -power lowvoltage CMOS A/D delta-sigma modulator for biopotential signals driven by a single-phase scheme," IEEE Trans. Circuits Syst. I, vol. 52, no. 12, pp , Dec Jae Hoon Shim; In-Cheol Park; Beomsup Kim;, "A third-order ΣΔ mod lator in 0 18-μm CMOS with calibrated mixed-mode integrators," Solid-State Circuits, IEEE Journal of, vol.40, no.4, pp , April Thao, N.T.;, "Asymptotic MSE law of nth-order ΣΔ mod lators Circ its and ystems II: Analog and Digital Signal Processing, IEEE Transactions on, vol.50, no.5, pp , May Kulchycki, S.D.; Trofin, R.; Vleugels, K.; Wooley, B.A.;, "A 77-dB Dynamic Range, 7.5- MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator," Solid-State Circuits, IEEE Journal of, vol.43, no.4, pp , April A. Gharbiya and D. A. Johns "On the implementation of input-feedforward delta-sigma modulator", IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp