Low Power Low Noise CMOS Chopper Amplifier

Transcription

1 International Journal of Electronics and Computer Science Engineering 734 Available Online at ISSN Low Power Low Noise CMOS Chopper Amplifier Parneet Kaur 1, Manjit Kaur 2, Gurmohan Singh 3 1 Student M.Tech VLSI Design, C-DAC Mohali 2 Engineer, C-DAC Mohali 3 Former Engineer, C-DAC Mohali 1 parneetsandhu@y7mail.com, 2 manjit_k4@yahoo.com, 3 gurmohan79@yahoo.co.in Abstract- Chopping is a proficient way to reduce the low frequency offset and 1/f noise in amplifiers. In this paper, a low power low noise CMOS chopper amplifier is presented. It is composed of a two stage amplifier. The first stage s high output impedance and the equivalent Miller capacitance of the second stage constitute together a low pass filter, which reduces the power consumption. The circuit of the presented amplifier is designed and simulated at 0.18µm CMOS Process and 1.8V supply. The simulation results show that the average power consumption is 44 µw. The chopper amplifier has a gain of 103.5dB and unity gain bandwidth of 100KHz. Keywords- Chopper amplifier; low pass filter; average power; 1. Introduction A low-noise and low power consumption amplifier has been a vital for detecting the small level signals. It is widely used in biomedical information systems. EEG (electroencephalogram) and ECG (electrocardiogram) have characteristics of low amplitude and low frequency [1, 2]. The bandwidth of the signal is from 0.3Hz to 100Hz and amplitude less than 100 µv and in case of EEG signals bandwidth is from 0.1Hz to 150 Hz and amplitude less than 5mV. These signals require precise designing of the acquisition and recording units for capturing and storing these signals. So the low noise, low power and the low offset amplifier are the key circuit for detecting the small signal levels in the biomedical information system. CMOS technology is used due to its low power consumption capability, dense integration and low cost. However, in CMOS technologies 1/f noise becomes a serious hindrance. It limits the minimum detectable signal at low frequency. So in order to design a high precision amplifier, chopping technique is used. It has low noise and low offset characteristics. It implements modulation technique which can be used to decrease Op-amp imperfections. 2. Principle of Chopper amplifier Op-amp imperfections such as noise input referred DC voltage can be reduced by chopping technique which makes use of Modulation. The principle of conventional chopper amplifier is illustrated in fig.1. With input, output and A is the gain of the linear memory less amplifier. The signal (t) and (t) are modulating and demodulating carriers with period T = 1/f where f chop is chopper frequency. Also V os and V n denote deterministic dc offset and noise. We can observe that the cut off frequency of the chopper amplifier should be higher than the chopping frequency so as no attenuation of the input signal occurs. This means large bandwidth and hence large power consumption. A post low pass filter is also needed to filter modulated noise, which consumes power too. Conventional chopper amplifier is very complex and consumes large power.

2 Low Power Low Noise CMOS Chopper Amplifier 735 Figure 1. Principle of chopper amplifier 3. Design of Chopper Amplifier It is clear; the conventional chopper amplifier needs a high cut off frequency than f chop and a post low pass filter. Figure 2: Chopper amplifier circuit This leads to large power consumption. The presented chopper amplifier circuit [3,4] is depicted in Fig.2. It compromises of a two stage amplifier, first stage is a folded cascode OTA amplifier, consists of a voltage cascaded current mirror to perform differential single ended conversion. The second stage is a common source amplifier with miller compensation which provides large output range. If we assume that the DC gain of the OTA is A, then the equivalent capacitance of (A+1) C c can be obtained at the output node of the operational amplifier, in accordance with the Miller theorem, where, C c is the Miller Capacitance. Also the cascade transistors of the first stage op-amp provides large output impedance which along with this Miller capacitance makes an low pass filter thereby eliminating the need of post low power filter. This helps to reduce the power dissipation.

3 3.1. Modulator Circuit design IJECSE,Volume1,Number 2 Parneet Kaur et al. The modulator [9] used in this circuit is composed of four switches, two NMOS and two PMOS. The input to the modulator is a sinusoidal wave (V signal ) which has maximum amplitude of 100µm. The switches are provided with square waves (Φ) of frequency double to that of input sinusoidal wave so that no signal aliasing occurs. Figure 3: Schematic of modulator circuit When Φ is high the NMOS switches are ON, PMOS are off so V out is V signal. When Φ is low PMOS switches are ON and NMOS switches are off, so V out = -V signal. Hence modulated waveform is obtained. The modulated output is shown in fig. 4. V signal suffers from clock feedthrough of modulator. This is very noisy in frequency domain,so dummy switches are used for compensation. Figure 4: Output waveform of the modulator circuit. 4. Simulation Results The Low Power Chopper Amplifier is designed in 180nm technology. The amplifier consumes maximum Power of 98.0 µw at 1.8V of supply. The DC open loop gain of the Chopper amplifier is db with phase margin of 58

4 Low Power Low Noise CMOS Chopper Amplifier 737 degree. Results are obtained without chopping also. Without chopping means when CLK1 is set to 1.8V and CLK2 is grounded. From the waveform in fig 7, we observe that the gain drops by few db s without Chopping. Figure 5: DC open loop gain curve for chopper amplifier.. Figure6: Phase margin of low power CMOS chopper amplifier is 58 degree. Figure 7: Reduced gain of the CMOS chopper aplifier with clock 2 grounded.

5 IJECSE,Volume1,Number 2 Parneet Kaur et al. The chopper amplifier consumes average power of 44 µw. The maximum and minimum power consumed by the chopper amplifier is 98µW and 15µW respectively. The fig. 8 shows power consumption waveform for the low power CMOS chopper amplifier. Figure 7: Power consumption results of Chopper amplifier. The input reffered power spectral Noise is nv, the input frequency is set to 5 KHz and the Chopping frequency is set to 10 KHz., we can see that the gain drops by few db s without Chopping and the noise of the amplifier also increases. The input reffered noise of the CMOS Chopper Amplifier with chopping is 32.47nV and without chopping is 1.06µV. From the waveforms in fig. 8 and fig. 9 we observe that the input referred power spectral density of the amplifier is smaller with chopping than without chopping. Figure 8: Input referred noise power spectral density with chopping.

6 Low Power Low Noise CMOS Chopper Amplifier 739 Figure 9: Input referred noise power spectral density without chopping. The table 1 below lists various specifications of the designed low power CMOS chopper amplifier. Table 1: Specifications of Low Power CMOS Chopper Amplifier Technology 180nm Gain (db) Phase (degree) 58 Unity Gain Bandwidth (KHz) 100 Average Power (µw) 44 Supply (V) 1.8V Input frequency (KHz) 5 Chopping frequency (KHz) Conclusion The chopper amplifier consists of two stage amplifier, the first stage comprises of cascaded current mirror in the OTA which leads to high impedence and the Miller capacitance of the second stage makes a low pass filter which elimates the need of an additional low pass filter in the circuit. The low pass filter formed by the OTA and the common source amplifier with Miller compensation eliminates the unwanted higher frequency components. CMOS Chopper amplifier is able to overcome dominant noise source of the differential input stage, for low frequency, ultra low amplitude signals.the whole amplifier consumes power of 98.4uW at a supply voltage of 1.8V, the equivalent input noise is 32.47nV. The chopper amplifier has a gain of 103.5dB and unity gain bandwidth of 100KHz. References [1] A. Bilotti and G. Monreal; Chopper-stabilized amplifiers with a track-and-hold signal demodulator, Vol. 46, No. 4, pp , April 1999 [2] J.F Witte,K.A.A Makinwa,and J.H.Huijsing, A CMOS Chopper Offset stabilized Opamp. IEEE Journal of Solid-state circuits,vol.42,no.11,pp ,2007. [3] Xiao Yang, Jing Yang, Li-fen Lin, Chao- dong Ling; Low -Power Low-noise CMOS Chopper Amplifier, in IEEE Coference,vol no.667,pp ,2011 [4] Xiao Yang, Yang Zhang, Wei- wei Huang, Chao- dong Ling ; Low- Power Chopper Amplifier without LPF, in IEEE Conference,vol no. 668,pp ,2011 [5] C.Menolfi and Q.Huang; A Fully integrated untrimmed CMOS instrumentation Amplifier with Sumicrovolt offset, IEEE J. Solid State Circuits,vol.34,no.3,pp ,March [6] M.S.J Steyart et.al. A Micropower Low-Noise Monolithic Instrumention Amplifier for Medical purposes, IEEE Solid State

7 IJECSE,Volume1,Number 2 Parneet Kaur et al. Circuits,vol.22,pp ,1987. [7] L. Toth and Y. Tsividis; Generalized chopper stabilization, vol-12, pp.i-540 to I-543, September [8] Christan C.ENZ, Gabor C. temes ; Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, CorrelatedDouble Sampling, and Chopper Stabilization, in IEEE proceedings,vol 186, pp , [9] C. Enz and G. C. Temes; Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization, Proc. IEEE,Vol. 84, No. 11, pp , November 1996.