An 8-Channel General-Purpose Analog Front- End for Biopotential Signal Measurement
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1 An 8-Channel General-Purpose Analog Front- End for Biopotential Signal Measurement Group 4: Jinming Hu, Xue Yang, Zengweijie Chen, Hang Yang (auditing)
2 1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
3 1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
4 Input Signal Characteristics Brain Brain Heart Muscle 5μV ~ 5mV DC~2 khz
5 System Overview 8 Differential Pairs
6 Battery Characteristic Source:
7 Block Diagram
8 1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
9 Pre-Amplifier Goals 1. Input noise cancellation a. Chopper modulation 2. Provides 40 db gain with 2 khz bandwidth 3. Adjustable cutoff frequency for different biopotentials
10 Pre-Amplifier Topology Fully differential folded cascode amplifier PMOS diff pair first stage, common source second stage Cross coupled configuration High CMRR
11 Open-loop Characteristics DC Gain Phase Margin Bandwidth 58 db 70 degrees 0-8 khz Output Voltage V
12 CMRR and PSRR 136 db from (0.5-2 khz) 90 db from (0.5-2 khz)
13 Chopper Implementation 1/f noise modulated to chopper frequency (15 khz) Subsequently eliminated by low pass filter
14 Adjustable High-pass Filter Nmos in series biased in subthreshold provides high resistance Tunable with gate voltage
15 Adjustable High-pass Filter
16 1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
17 OTA Used in Gm-C Filter
18 2nd-Order Programmable Gm-C Filter gm4 gm1 gm2 gm3 Gm2 used to set cutoff frequency -biasing voltage is varied
19 Adjustable Low Pass Filter Cutoff frequency can vary from 255 Hz to 2.4 khz Capacitor at 3n -a bit large
20 Full Pre-amplification Stage 40 1kHz Input
21 Pre-Amp and Gm-C Bandpass Response
22 Noise Analysis ~2.24μVrms in (0.5-2 khz)
23 Full Circuit
24 Performance Benchmarking
25 1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
26 Channel Selector Logic Data Select Signals Output D 2 D 1 D 0 Y S S S S S S S S7 Channel Selector
27 Channel Selector Logic Channel Selector
28 Channel Selector Logic Output Bit 0, 4, 7 Channel Selector
29 Buffer - Differential Difference Amplifier Buffer
30 DDA Open-loop Frequency Response Buffe r
31 DDA Close-loop Frequency Response Buffer
32 1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter Channel Selector & Buffer 5. Programmable Gain Amplifier and BGR 6. Analog-Digital Converter
33 Bandgap Reference Generator Vbiasn = 0.75 V; Vbiasp = 2.3 V PGA
34 PGA Attempted Topology PGA
35 PGA Attempted Topology Can only reach a gain of 1. Moved to other typology. PGA
36 PGA Topology Fully differential sample and hold circuit from homework assignment. Fully differential amplifier comes from Baker CH CH CF CF CH A = 1+CF/CH PGA
37 Amplification Signal, Gain = 2 PGA
38 Amplification Signal, Gain = 10 fclock = 500 K Vin f = 2K PGA
39 SW Cap Amp -- Clock Signals ph1, ph2, ph3 are non- overlapping. --A 5-transistor op-amp with a gain =1 transferring the fully differential amplifier s output signals into single ended signals to the ADC. PGA
40 1. System Specifications & Structure 2. Chopper Low-Noise Amplifier 3. Programmable Low-Pass Filter Channel Selector & Buffer 5. Programmable Gain Amplifier 6. Analog-Digital Converter
41 ADC Architecture 8-bit SAR ADC Comparator SAR Logic Binary Weighted Capacitive DAC Charge Redistribution Architecture No s/h circuit Approaches Vcm at end of cycle
42 Comparator Design Output range ICMR Power Propagation Delay Rail to Rail V < 396 uw 2.5 ns ADC
43 Comparator Layout
44 SAR Logic Schematic ADC
45 SAR Logic Layout ADC
46 DAC Schematic 1. Sampling phase 2. Hold phase 3. Charge redistribution phase ADC
47 One Throw Three Pole Switch Design ADC
48 ADC Conversion Cycle Voltage =.309 Digital Code = ADC
49 Results Dynamic Range 0 V -2.0 V Power Consumption 478 μw ADC
50 Conclusion -- Collects EEG, ECoG, EMG, ECG signal from probes; --Processes EEG, ECoG, EMG, ECG signal for μc; -- Low power consumption (~890μW, ~270μA, 3.3V) -- Portable ready
51 Future Work -- Adding control abilities on channel switching; -- Review the order of system blocks; -- Possible power optimization; -- Command library; -- Integration of the voltage regulator (risky: heat diss.)
52 Block Diagram
53 Questions?
An 8-Channel General-Purpose Analog Front-End for Biopotential Signal Measurement
An 8-Channel General-Purpose Analog Front-End for Biopotential Signal Measurement Xue Jinming Yang, Hu, Jinming Xue Yang, Hu, Zengweijie Chen, Hang Yang Abstract This paper presents system level specifications
An 8-Channel General-Purpose Analog Front-End for Biopotential Signal Measurement
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