A Modified Structure for High-Speed and Low-Overshoot Comparator-Based Switched-Capacitor Integrator

Transcription

1 A Modified tructure for High-peed and Low-Overshoot Comparator-Based witched-capacitor Integrator Ali Roozbehani*, eyyed Hossein ishgar**, and Omid Hashemipour*** * VLI Lab, hahid Beheshti University, G.C., Tehran, Iran, a.roozbehani@mail.sbu.ac.ir ** Microelectronic Lab, hahid Beheshti University, G.C., Tehran, Iran, h_pishgar@sbu.ac.ir *** Department of Electrical and Computer Engineering, hahid Beheshti University, G.C., Tehran, Iran, hashemipour@sbu.ac.ir Abstract: In this paper, a simpler and faster comparator-based switched-capacitor (CBC) architecture than the conventional CBC circuits is presented. A voltage dependent current source is used to improve the performance of the CBC integrator. Also, the preset phase is modified to increase the sampling frequency. A CBC integrator is designed and simulated in 18nm CMO technology with 1.8V supply voltage to verify this method. The input signal frequency of sinusoidal wave and the sampling frequency are 2 khz and 1 MHz, respectively. Keywords: Comparator-Based witched-capacitor circuits, Comparator, data converters, Integrator, Voltagecontrolled current source. 1. Introduction The miniaturization of the transistor capability in the CMO technology and the subsequent supply voltage reduction are the most important factors of the analog circuiesign difficulty in the recent technologies. The operational amplifier is used the widely device in the analog and the mixed signal circuits. But, the operational amplifiers in the sub-micron technologies [1] suffer the low gain, limited dynamic range and swing, high power consumption, stability and compensation considerations, large chip area, etc. The comparator-based switchedcapacitor technique was presented in [1] to overcome these drawbacks. In this method, the op-amp is replaced by a comparator, two current sources and logic block. The CBC circuits are based on detection of the virtual ground condition unlike the opamp-based switchedcapacitor (OBC) circuits which the virtual ground condition is imposed between two nodes. The overshoot error in the output node is caused by the inherenelay of the comparator and the logic block. Also, increasing of the overshoot error can reduce the sampling frequency. The comparator delay compensation by it s threshold shift [1,2], adding a switch-capacitor overshoot compensator [3], adding an intermediate phase with the smooth current to decrease the slope of the output voltage [4] and extra comparator [5] were suggested to reduce the overshoot error. Also, in [6], the preset phase was removed and two pairs of the current sources are used to decrease the duration of the charge transfer phase. An additional clock is used to reduce control circuielay in [7]. Although these methods have made some improvements, but the circuit has been complicated. The proposed method in this paper has an improved performance and simple circuit together. In this paper, a conventional CBC integrator is described in the section 2. The proposed method to improve of the CBC structure is presented in the section 3. Finally, simulation results and conclusion are given in sections 4 and 5, respectively. 2. Basis of the CBC Integrator CBC integrator and its signal diagram are shown in Fig. 1. The and signals are non-overlapping clocks. In sampling phase, when the phase is High, C 1 is charged to V in -. In the charge transfer phase, the phase is Low and the phase is High, so charge on C 1 is transferred to C 2. The phase is composed of three subphases: (1) reset, (2) Coarse and (3) Fine charge transfer. The logic block can work correctly when the is Low. In the preset phase, when the and switches are closed concurrently, the output node is connected to the lowest voltage of the circuit and <. In the end of the preset phase, the E1 phase is High and the coarse current source (I 1 ) is turned on, so is charged up. The rises until the reaches and crosses the. o, the state of the comparator changes, hence the E1 and E2 are Low and High, respectively. The comparator and the logic block have an inherenelay. According to the large value of the I 1 and total delay ( ) of the circuit, an overshoot error in the output voltage as is occurred. The E2 turns on the fine current source (I 2 ) which is smaller than I 1, to reduce the overshoot error. I 2 discharges the, so falls. When crosses, the output of the comparator switches Low and I 2 turns off. At the end of the phase, simultaneous with the changing state of the comparator, the switch is opened. Thus, the stored charge on the and its voltage remain constant and charge transfer phase is completed.

2 C 2 V E in 1 I 1 C 1 Logic I 2 [ n] - (a) [ n] [n] - V x Fig. 1: The CBC integrator and its signals 3. roposed CBC Integrator The overshoot error in the output voltage is discussed in details and a new architecture for CBC circuit based on voltage controlled current source is presented in this section. Also, the preset phase is modified to increase the sampling frequency. 3.1 The overshoot error The linear coarse current source in conventional CBC structure and the total delay of the circuit are the major reasons of the overshoot error in the output voltage. If the coarse current is large, the fine current has to turn on longer to establish the virtual ground condition. On the other hand, if the coarse current is small, it have to turn on longer to reach the to the and create the virtual ground condition. o there is a trade-off between speed and overshoot error. The proposed method in this paper to improve this error is based on non-linear current source. The linear and non-linear current source comparison is shown in Fig. 2. The large current is applied to charge up the load capacitor at the start of the coarse phase in non-linear coarse current source. When the output voltage is raised, the coarse current is reduced. o, the small current is flow gradually to the circuit when is near the. Therefore, the overshoot error in the output voltage can be less than the linear coarse current source. Also, there is no trade-off between the overshoot error and the sampling frequency unlike the linear coarse current source. - Fig. 2: The output voltage in (a) the linear coarse current sources and the non-linear coarse current Voltage-current equation of a MO transistor is given by: 2 ( ) ( 1 λ ) I = β V V V (1) D G TH D Where, I D is drain current, β is transconductance parameter, V G is source-gate voltage, V TH is MO threshold voltage, V D is source-drain voltage and λ is channel length modulation parameter. According to Equation (1), the MO drain current can be controlled by V G and V D. Firstly, V G is considered. As shown in Fig. 3, the changes of the output voltage should be applied to the gate of as a feedback. The feedback path is a critical part in the proposed method because, a precise design of that can decreases the overshoot error and so eliminates the fine current source. out in Fig. 3: Applying feedback to control I 1 current The variation range of the output voltage is variable in the different periods. Against, the range of the is between a lower voltage than and, so as shown in Fig. 4, it can be applied to gate of with a level shifting circuit to increase of the for creating a desire current value of the coarse current source. The current value is set by negative feedback circuit which consists of the level shifter, C 2 and. At the end of the preset phase, is less than the. o, at the start of the, turns on and is charged by a relative large current. Gradually, while the load capacitor is charging, the and are raised and this growth is led to the gate of by the level shifter. In addition, the V G and V D are decreased by increasing of the output voltage, so drain current of is lowered. This cycle continues until the reaches the and the switch opens.

3 C 1 V in Logic C 2 Voltage Level hifter source that is turned on by signal. The current value of the current source depends on some factors such as the input signal frequency, the sampling frequency, the duration of the preset phase and the equivalent capacitance from the node. The preset current is obtained by the following equation: Fig. 4: Voltage-controlled current source mechanism integrator The voltage level shifter can be implemented by using two consecutive inverters as shown in Fig. 5. The dimensions of the transistors were chosen to linearize the circuit characteristic at the desired input range. V IN 2 1 V OUT1 M 22 M 21 V OUT ΔV I p = C (3) t p where CC 1 2 C = CL C1 C2 (4) and Δ V C1 = V in ( nt ) C 2 (5) and t is the duration of the preset phase. The implementation of the preset current source is illustrated in Fig. 7. Fig. 5: The voltage level shifter implementation 3.2 Low speed According to the previous section, the fine current source removed, so the time of the charge transfer phase was saved. Also, the charge transfer phase can be reduced by some other changes. At the preset phase, is connected to the lowest voltage of the circuiirectly and is discharged completely, so < condition is established. During, is charged to the (nt) (the final value of the output voltage in a period). The (nt) is given by the following recursive equation [8]: 1 V out (( n 1) T ) = C V in ( nt ) V CM V out ( nt ) C (2) 2 Where, n is an integer, T is or period, V in (nt) is the input voltage and is the common mode voltage. According to the Equation (2), the output voltage changes in each period are equal to the first term on the right side. Therefore, in the preset phase, if is discharged little more than this term, the will be less than ( < ). Fig. 7: The preset current source, (a) circuit symbol, transistor level implementation 4. imulation Results The simulation results of the CBC integrator with the proposed voltage-controlled current source is given in Fig. 8. The input signal and the sampling frequency are a 2 khz sinusoidal wave and 1 MHz, respectively. Vin(V) (a) I V B M C 2 Voltage Level hifter C 1 V in Logic Fig. 6: The preset phase modification As depicted in Fig. 6, this scheme has been implemented by replacing the switch by a current I Fig. 8: Integrator circuit input and output waveforms modified by adding the voltage level shifter only. Also, the output voltage waveforms are compared in 9 for the CBC integrator with four different structures.

4 (a) Vin(V) (c) (d) (e) Fig. 9: The CBC integrator output waveform comparison, (a) the input signal, and the output signal of conventional structure, (c) VCV is added, (d) preset is modified and (e) both current source and preset are modified (proposed CBC integrator) A summary of the proposed integrator performance is presented in Table I. TABLE I: ummary of the Integrator erformance The phase of the output voltage in the different frequencies of the input signal and the corresponding sampling frequency for the proposed CBC integrator is summarized in Table II. Technology upply Voltage Input Frequency ampling Frequency ower Consumption THD.18μm CMO 1.8 V 2 khz 1 MHz 24μW -43.7dB TABLE II: The Output Voltage hase for the Different Input and ampling Frequencies Input ignal Freq. (khz) ampling Freq. (MHz) Output ignal hase (deg) Also, the input and output signals of the proposed CBC integrator are shown in Fig. 1. In this figure, the input and the sampling frequencies are 2 khz and 1 MHz, respectively. Vin(V) 5. Conclusion The proposed structure was reduced the circuit complexity with the simplifying of the current source design. A voltage dependent current source was used to realize the non-linear coarse current source. Therefore, the overshoot error of the output was reduced and the requirement of the fine current source was resolved. Also, by removing the fine current source and modification of the preset phase, the circuit ability to work at higher frequencies was provided. Finally, to verify the proposed architecture, a CBC integrator was simulated in 18nm CMO technology with 1.8V supply voltage. The results confirmed the integration process of the proposed integrator circuit. Fig. 1: The input and output signals of the proposed CBC integrator (fin=2 khz, fs=1 MHz)

5 References [1] J. K. Fiorenza, T. eppke, C. G. odini,. Holloway, and H.-. Lee, Comparator-based switched-capacitor circuits for scaled CMO technologies, IEEE J. olid-tate Circuits, vol. 41, no. 12, pp , Dec. 26. [2] C. Wulff, T. Ytterdal, CBC pipelined ADC with comparator preset, and comparator delay compensation, norchip, 29, pp [3]. K. hin, Y.. You,. H. Lee, K. H. Moon, J. W. Kim, L. Brooks, and H.. Lee, A fully-differential zero-crossing-based 1.2V 1b 26M/s pipelined ADC in 65nm CMO, in VLI Circuits, 28 IEEE ymposium on, 28, pp [4]. Y. Mortazavi, A. Nabavi, and. Amiri, High-accuracy Comparator-Based witched-capacitor tructure, IEICE Electronic Express, vol. 7, no. 5, [5] K. F. Wong,. W. in,.. U, R.. Martins, A Modified Charging Algorithm for Comparator-Based witched-capacitor Circuits, IEEE International Midwest ymposium on Circuits and ystems, 29. [6] F. A. arsan, A. Ayatollahi, A Comparator-Based witched- Capacitor Integrator Using a New Charge Circuit, OC Conference, roceedings of the 12th IEEE International Multitopic Conference, December 23-24, 28. [7] M. Zamani,. J. Ashtiani, M. Dousti and M. N. Moghadasi, A 12b, 4-M/s, 4.1mW Fully Differential ipelined ADC in.18μm CMO, IEICE Electronic Express, vol. 7, no. 23, [8] J. Ouyang, A Comparator-Based witched-capacitor Delta igma Modulator, M. Eng. thesis, Massachusetts Institute of Technology, Massachusetts, August 29.