Fig. 2. Schematic of the THA. M1 M2 M3 M4 Vbias Vdd. Fig. 1. Simple 3-Bit Flash ADC. Table1. THA Design Values ( with 0.

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1 A 2-GSPS 4-Bit Flash A/D Converter Using Multiple Track/Hold Amplifiers By Dr. Mahmoud Fawzy Wagdy, Professor And Chun-Shou (Charlie) Huang, MSEE Department of Electrical Engineering, California State University, Long Beach, CA 90840, U.S.A. ABSTRACT - Flash A/D converters (ADCs) play an important role in many applications, such as radar systems, aerospace applications, etc. A typical flash ADC includes only one track/hold amplifier (THA), however, in this paper a multi-tha topology is presented and investigated, where one THA is connected to every comparator. A comparative study is performed employing a 4-Bit ADC; this includes measuring the integral nonlinearity (INL) for both architectures at different frequencies. Behavioral modeling using Verilog-A is used to quantify the accuracy of the circuits. The ADCs under consideration were implemented using Cadence 0.18µm CMOS process. I. INTRODUCTION The flash ADC architecture is the fastest one of all ADCs. An n-bit flash ADC consists of 2 n -1 comparators. A simple 3-bit flash ADC is shown in Fig. 1. Conversion speed is limited by the sampler (THA) frequency response and the comparators input capacitances. Since many comparators are required, ADCs with resolutions higher than 8 bits rarely use the flash architecture. of comparators connected to Vin, i.e. a large capacitive load at the input of the track/hold amplifier (THA), thus limiting the ADC speed. For Vref =1V and and a 4-bit ADC, the quantizing step size (1LSB) is 62.5mV. A severe limitation in very high-speed converters is meta-stability [2], which is caused by the finite gain in the comparators. Therefore, it is common to use comparators with a pre-amplifier followed by a regenerative latch. II. FLASH ADC COMPONENT DESIGNS 1. Track-and-Hold Amplifier (THA) The function of the THA is to sample an analog input signal and hold the sample value over a certain length of time for subsequent processing Circuit Operation and Design Values: Fig. 2 shows the schematic of the THA circuit [3]. Design parameters of the transistors M1, M2, M3, and M4 are given in Table 1 below. Fig. 2. Schematic of the THA Fig. 1. Simple 3-Bit Flash ADC ADCs are characterized by differential nonlinearity (DNL) and integral nonlinearity (INL) [1]. Input capacitive loading results from having a large number 1 M1 M2 M3 M4 Vbias Vdd W=100µ W=50μ W=50μ W=100μ 1.4V 1.8V Table1. THA Design Values ( with 0.18µm lengths) 1.2. Output Waveforms for an AC Input: Simulations were performed for the THA at various frequencies. Fig. 3 shows the response to a 1GHz sinusoidal input with a 2GHz clock.

2 Fig. 3. Simulation Result of THA (Fin=1GHz, Fclk=2GHz) Fig. 5. Frequency Response of the THA η 1.3. Output Waveforms for a DC Input: In order to test the THA accuracy, a DC input is applied. Various DC inputs of 0.3V, -0.3V, 0.9V, and -0.9V were applied with clock frequencies of 10MHZ, 100MHz, and 1GHz. Fig. 4 shows the response to a 0.9V dc input at a 1GHz clock frequency. η 2 Fig. 6. The Proposed Comparator Circuit [4] M1 10μ M8 50μ M15 30μ M22 30μ M2 10μ M9 50μ M16 30μ M23 10μ M3 10μ M10 160μ M17 10μ R1 200K Fig. 4. Simulation Result of THA (DC Input = 0.9V, Fclk=1GHz) 1.4. Frequency Response of the THA in the Track Mode: The 2 THA must meet the accuracy requirement of ADC, i.e. < 0.5LSB. In a 4-bit flash ADC, the error is < 0.5 (2-4 ), i.e. <2-5, or <3% (1) For Vref =1V, Fig. 5 shows an error of 30mV (i.e. 1V 970mV), at 2.62GHz, which meets the ADC requirement of 2GSPS operation. 2. Comparator The comparator is the most important component in the ADC Circuit Operation and Design Values: The circuit consists of parallel differential-input pre-amplifiers followed by a regenerative latch [4], as shown in Fig. 6. Design values are given in Table 2. 2 M4 10μ M11 150μ M18 10μ R2 200K M5 160μ M12 150μ M19 20μ RT 1.5K M6 150μ M13 50μ M20 30μ M7 150μ M14 50μ M21 10μ Table 2. Design Values of the Comparator (Device Widths Shown, All Device Lengths are 0.18µm) It can be shown that the latch-mode time constant is given by [5]: ح ltch = C L /G m (2) where C L is the load capacitance at the regenerative nodes η 1 and η 2, and G m is the transconductance of each inverter. To achieve low offset voltage, one solution is to use large differential input transistors for comparator. According to [6], the standard deviation of offset voltage is inversely proportional to the square root of

3 the area, i.e. σ offset WL Comparator Simulation Results: Various simulations were performed using sinusoidal inputs with frequencies of 5MHz, 50MHz, 500MHz, and 1GHz, and clock frequencies of 10MHz, 100MHz, 1GHz, and 2GHz respectively. Fig. 7 is an example simulation which also illustrates the delay between the input and output of the comparator. Fig. 7. Simulation Result of Comparator (Fin=500MHz, Fclk=1GHz) The delay times (rise time t r and fall time t f ) of the above-mentioned simulation cases were measured. Table 3 shows that the time delay is almost proportional to the clock period at lower signal frequencies. As frequency increases, the delay time increases disproportionately (e.g. 46% at a signal frequency of 1.3GHz and a clock frequency of 2.6GHz). For proper operation of the comparator, and hence the entire ADC, the delay time should be kept at a reasonably small fraction of the input signal period. Therefore, to be on the safe side, the maximum input and clock frequencies may be limited to 1GHz and 2GHz respectively, thus the comparator meets the requirements of a 2GSPS ADC. 3. Priority Encoder This block processes the thermometer code at the 15-comparator outputs (A 14 -A 0 ) where A 0 is the LSB and A 14 is the MSB. The output binary is 4 bits with b 0 and b 3 as the LSB and MSB respectively. The design is based on following equations [7]: b 0 = AA 0 1' + AA 2 3'+ AA 4 5' + AA 6 7' + AA 8 9'+ A10A11'+ A12A13'+ A14 b 1 = AA 1 3'+ AA 5 7'+ AA 9 11'+ A13 b 2 = AA 3 7'+ A11 b 3 = A7 (3) III. CADENCE-SPECTRE SIMULATION RESULTS OF THE ADC USING SINGLE OR MULTIPLE THAs The multiple-tha Flash ADC is shown in Fig. 8; it consists of 15 comparators using a 2V reference voltage, as well as 15 THAs. The INL is measured for both the single-tha ADC and the multi-tha ADC at frequencies of 100MHz, 500MHz, 1GHz, 1.1GHz, 1.2GHz, and 1.3GHz to compare their performances. To that end, a ramp voltage ranging from 0 to 2V is applied. For example, in the 100MHz case, the ramp duration is 16*10ns. Some example INL results are shown below. fin fclk Delay(tr) Delay(tf) period delay/period 5MHz 10MHz n n 200ns MHz 100MHz n 2.002n 20ns MHz 1GHz p p 2ns GHz 2GHz 0.24n 0.277n 1ns GHz 2.2GHz 0.32n 0.31n 0.9ns GHz 2.4GHz 0.34n 0.32n 0.83ns GHz 2.6GHz 0.35n 0.37n 0.76ns 0.46 Table 3. Delay Times of the Comparator at Various Frequencies 3 Fig. 8. Schematic of Multi-THA 4-Bit Flash ADC 1. INL Simulation Results with Fin=100MHz and Fclk=200MHz Simulation results for both single-tha ADC and multi-tha ADC are given in Figs. 9 and 10 respectively.

4 Fig. 9. INL Simulations (Fin=100MHz, Fclk=200MHz, Single-THA Flash ADC) Fig. 12. INL Simulations (Fin=1GHz, Fclk=2GHz, Multi-THA Flash ADC) from 0.9LSB to 0.6LSB. Thus the multi-tha ADC topology becomes more effective as signal frequency increases. The INL results of the above simulations as well as other simulations are all summarized in Table 4. The table confirms the above observations regarding the effectiveness of the multi-tha ADC versus the single-tha ADC, even with a fixed clock frequency of 2GHz. Fig. 10. INL Simulations (Fin=100MHz, Fclk=200MHz, Multi-THA Flash ADC) 2. INL Simulation Results with Fin=1GHz and Fclk=2GHz Simulation results for both single-tha ADC and multi-tha ADC are given in Figs. 11 and 12 respectively. IV. BEHAVIORAL MODELING SIMULATION RESULTS OF THE ADC USING SINGLE OR MULTIPLE THAs Behavioral modeling is used to describe circuit performance at the block diagram level without getting into the circuit details. However, in our case, behavioral modeling is Signal Frequency Clock Frequency Single-THA Multi-THA 100M 200M -0.5LSB -0.4LSB Fig. 11. INL Simulations (Fin=1GHz, Fclk=2GHz, Single-THA Flash ADC) 500M 1G 0.6LSB 0.4LSB 1G 2G 0.9LSB 0.6LSB 1.1G 2.2G -0.9LSB 0.8LSB 1.2G 2.4G 0.9LSB 0.7LSB 1.3G 2.6G -1LSB 0.9LSB 100M 2G 0.3LSB 0.2LSB 500M 2G 0.4LSB 0.3LSB 1G 2G 0.9LSB 0.6LSB Table 4. Statistics of Worst INL The simulations of Figs reveal that using multi-tha versus single-tha improves the worst INL from 0.5LSB to -0.4LSB at an input frequency of 100MHz, whereas at 1GHz the improvement is 4 performed at specific frequencies, and at each frequency the THA has a different gain. The value of this gain is obtained using the Cadence-Spectre simulations, then substituted into the algorithm to determine INL; the purpose is to verify the

5 measurement procedure according to the following steps: 1. Apply sinusoidal input, find the frequency response of the single-tha and the multi-tha, then determine their gains (X and Y respectively) at the frequencies under consideration as shown in Tables 5 and 6 respectively. Note that the THA in the single-tha ADC has a capacitive load equal to the sum of input capacitances of all comparators, whereas the THA in the multi-tha ADC has a capacitive load equal to a single comparator input capacitance. 2. Use the X and Y values of Tables 5 and 6 to form gain blocks in the Verilog-A representation of THAs at different frequencies. 3. Use Verilog-A to code the behavior of comparators. 4. Incorporate gain and comparator blocks in the ADC. 5. Compute the INL at different frequencies. Fin (Sine Wave) X 100Mhz Mhz Ghz Table 5. Gain of Single-THA at Different Frequencies Fin (Sine Wave) Y 100Mhz Mhz Ghz Table 6. Gain of Multi-THA at Different Frequencies Fig. 14. INL Simulations for Multi-THA ADC Behavioral Modeling (Fin=100MHz, Fclk=200MHz) The simulations of Figs. 13, 14 reveal that using multi-tha or single-tha gives slightly different INL shapes but almost the same worst INL of LSB at an input frequency of 100MHz. But at an input frequency of 1GHz, the simulations of Figs. 15, 16 reveal that using multi-tha versus single-tha improves INL for most of the dynamic range including a slight improvement of the worst INL from 0.57 LSB to LSB. Comparing Figs. 9, 13 on the one hand and Figs. 10, 14 on the other hand reveals that Spectre-based results and Verilog-based results at an input frequency of 100MHz have the same shape with slight differences in INL values throughout the ADC dynamic range, i.e. a reasonable agreement between circuit simulation results and behavioral modeling results. 2. INL Behavioral Modeling Simulation Results with Fin=1GHz and Fclk=2GHz 1. INL Behavioral Modeling Simulation Results with Fin=100MHz and Fclk=200MHz Fig. 15. INL Simulations for Single-THA ADC Behavioral Modeling (Fin=1GHz, Fclk=2GHz) Fig. 13. INL Simulations for Single-THA ADC Behavioral Modeling (Fin=100MHz, Fclk=200MHz) However, comparing Spectre-based results with Verilog-based results at an input frequency of 1GHz reveals some noticeable differences between Figs. 11, 15 (single-tha) but small differences between Figs. 5

6 Fig. 16. INL Simulations for Multi-THA ADC Behavioral Modeling (Fin=1GHz, Fclk=2GHz) 12, 16 (multi-thas), namely same shape with slight differences in INL values throughout the ADC dynamic range, i.e. a reasonable agreement between circuit simulation results and behavioral modeling results. V. CONCLUSIONS The paper showed the design of a 2-GSPS 4-bit flash ADC; design details were given in [8-10] for individual components i.e. THA, comparator, and priority encoder. Simulation results using Cadence- Spectre with 0.18µm CMOS process for both the THA and comparator were performed covering a wide range of input frequencies and clock frequencies. Both the THA and the comparator meet the requirements of an ADC working at 2GSPS. Extending the frequency range of flash ADCs is a highly desirable issue for a number of strategic applications. However, in the RF range, the flash ADC frequency response is degraded mainly due to the sum of input capacitances of all comparators which degrade the THA performance. Therefore, the paper presents a novel technique which employs a bank of (2 n -1) THAs such that each THA is connected to a comparator. Simulation results using Cadence-Spectre verified that INL improves at higher frequencies due to using a multi-tha ADC versus a single-tha ADC. This improvement also consistently increases versus frequency, which means that the new technique provides a bandwidth extension for the ADC at the expense of some more hardware, namely the additional THAs. Behavioral modeling was performed to verify circuit simulations by replacing the comparators and the priority encoder with frequency-independent blocks; THAs were represented by fixed gain blocks using the gains at specific frequencies extracted from 6 Spectre simulations. INL was computed as was done in [11] and [12]. Behavioral modeling results had a reasonable agreement with circuit simulations; the limited discrepancies at the GHz range may be mainly attributed to the actual frequency responses of the comparators and the priority encoder, which were originally modeled by frequency-independent blocks. VI. REFERENCES [1] R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, 2 nd Edition, IEEE Press (Wiley Interscience), [2] C.L. Portmann, and T.H. Y. Meng Power- Efficient Metastability Error Reduction in CMOS Flash A/D Converters, IEEE Journal of Solid-State Circuits, Vol. 31, No. 8, August [3] M.Choi and A. Abidi, A 6-b 1.3-Gsample/s A/D Converter in 0.35-μm CMOS IEEE Journal of Solid-State Circuits, Vol.36, No.12, Dec [4] H. Pekau, L. Hartley and J.W Haslett, A Re-configurable High-Speed CMOS Track and Latch Comparator with Rail-to-Rail Input for IF Digitization, IEEE Intl. Symposium on Circuits and Systems (ISCAS), pp , [5] D. A. Johns and K. Martin, Analog Integrated Circuit Design, New York, NY: Wiley, [6] Pelgrom, M.J.M.; Duinmaijer, A.C.J.; Welbers, A.P.G.; Matching properties of MOS Transistors, IEEE J. of Solid-StateCircuits, Vol. 24, No. 5, pp , Oct [7] M. F. Wagdy and Q. Xie, Comparative ADC Performance Evaluation Using a New Emulation Model for Flash ADC Architectures, IEEE 37th Midwest Symp. on CAS, Lafayette, Louisiana, pp , August 3-5, [8] K. Uyttenhove and M.S. J. Steyaert A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25-um CMOS, IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, July [9] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, [10] P. E. Allen and D. R. Holberg CMOS Analog Circuit Design New York: Oxford, [11] M. F. Wagdy and Z. Liu, An 8-Bit, 20 MSPS Pipelined ADC, Proc. of the 46 th IEEE Midwest Symp. on CAS, Cairo, Egypt, Dec , [12] V. Do and M. F. Wagdy, A 12-Bit, 3-Bits Per Stage, CMOS Pipelined ADC Architecture, IEEE 1st Intl. Comp. Eng. Conf. (ICENCO 2004), Cairo University, Egypt, pp , Dec , 2004.