PAPER A 10 b 200 MS/s1.8mm 2 83 mw 0.13 µm CMOS ADC Based on Highly Linear Integrated Capacitors

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1 IEICE TRANS. ELECTRON., VOL.E90 C, NO.10 OCTOBER PAPER A 10 b 200 MS/s1.8mm 2 83 mw 0.13 µm CMOS ADC Based on Highly Linear Integrated Capacitors Young-Ju KIM, Young-Jae CHO, Members, Doo-Hwan SA, and Seung-Hoon LEE a), Nonmembers SUMMARY This work proposes a 10 b 200 MS/s 1.8mm 2 83 mw 0.13 µm CMOS ADC based on highly linear integrated capacitors for highquality video system applications such as next-generation DTV and radar vision and wireless communication system applications such as WLAN, WiMax, SDR, LMDS, and MMDS simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC optimizes chip area and power dissipation at the target resolution and sampling rate. The proposed ADC employs two versions of the SHA with gate-bootstrapped NMOS switches and conventional CMOS switches to verify and compare the input sampling effectiveness. Both of the two versions of the wide-band low-noise SHA maintain 10 b input accuracy at 200 MS/s. The proposed all signal-isolated 3-D completely symmetric capacitor layout reduces the device mismatch of two MDACs by isolating each unit capacitor from all neighboring signal lines with all the employed metal lines and by placing extra internal metal lines with a fixed internal bias voltage between signal lines connecting the bottom plate of each unit capacitor. The low-noise on-chip current and voltage references with internal RC filters can select optional off-chip voltage references. The prototype ADC is implemented in a 0.13 µm 1P8M CMOS process. The measured DNL and INL are within 0.24 LSB and 0.35 LSB while the ADC shows a maximum SNDR of 54 db and 48 db and a maximum SFDR of 67 db and 61 db at 200 MS/s and 250 MS/s, respectively. The ADC with an active die area of 1.8 mm 2 consumes 83 mw at 200 MS/s and at a 1.2 V supply. key words: ADC, CMOS, 3-D symmetric layout, low power, low voltage 1. Introduction The recent advance of deep submicron- or nanometerscale device manufacturing technologies and super highspeed digital signal processing techniques has accelerated the System-on-a-Chip (SoC) trend to integrate many complicated analog and digital VLSI circuits in a single chip. High-resolution, high-speed, low-cost CMOS A/D converters (ADCs) for critical system interface have also been in high demand. Particularly, the ADCs for high-quality video displays and wireless communication systems such as nextgeneration Digital TV (DTV) with Ultra extended Graphics Array (UXGA) resolution, radar vision, IEEE based Wireless Local Area Network (WLAN), IEEE based Worldwide Interoperability for Microwave Access (WiMax), Software Defined Radio (SDR), Local Multipoint Distribution Service (LMDS), Multi-channel Multipoint Distribution Service (MMDS), and various highperformance test equipment require a resolution of 10 b level and a sampling rate exceeding 200MS/s simultane- Manuscript received January 10, Manuscript revised May 7, The authors are with the Department of Electronic Engineering, Sogang University, Seoul , Korea. a) hoonlee@sogang.ac.kr DOI: /ietele/e90 c ously with low voltage, low power, and small chip area. Of various conventional ADC architectures, the pipeline architecture has been widely employed to obtain the required performance of a 10 b resolution and a sampling rate exceeding 200MS/s and simultaneously to optimize power consumption and chip area. The proposed ADC and the recently reported 10 b CMOS ADCs with a sampling rate exceeding 50 MS/s are compared in Fig. 1 [1] [19]. As illustrated in Fig. 1, most of the ADCs are based on a multi-bit-per-stage pipeline architecture with more than four stages guaranteeing high-speed operation due to a decreased closed-loop gain and a reduced load capacitance of inter-stage amplifiers. However, the power consumption and chip area of the ADCs may be increased with more pipeline stages and the static and dynamic performance may be considerably degraded due to input-referred errors and device mismatches from back-end pipeline stages [18]. On the other hand, a two-stage pipeline architecture which decides 6 b and 5 b from each stage consumes less power and occupies smaller chip area than a multi-bit-perstage pipeline architecture due to the reduced number of amplifiers while it is difficult to achieve a sampling rate of 200 MS/s level at 10 b accuracy due to the high closed-loop gain and load capacitance of inter-stage amplifiers [13]. A parallel pipeline architecture has also been adopted to obtain a sampling rate of several hundred MHz [15], [16], [19]. However, the parallel pipeline architecture may increase the active die area and require additional circuit design techniques to reduce mismatches and offsets between independent channels. Considering the above-mentioned design issues, the Fig. 1 Sampling rate and power consumption of recently reported 10 b CMOS ADCs. Copyright c 2007 The Institute of Electronics, Information and Communication Engineers

2 2038 IEICE TRANS. ELECTRON., VOL.E90 C, NO.10 OCTOBER 2007 proposed ADC adopts a three-stage pipeline architecture to optimize power consumption and chip area and to reduce the input-referred noise and device mismatch from backend stages by reducing the number of inter-stage amplifiers at the required sampling rate of 200 MS/s. As shown in Fig. 1, the proposed ADC demonstrates a power consumption of 0.42 mw/mhz at a 1.2 V supply voltage and 200 MS/s, which is close to the highest value in the world. The proposed 10 b 200 MS/s0.13µm CMOS ADC implements (1) a three-stage pipeline architecture to minimize power and chip area, (2) both of gate-bootstrapped NMOS switches and conventional CMOS switches to verify and compare the input sampling effectiveness of the Sample-and-Hold Amplifier (SHA) at a 1.2 V supply, (3) all signal-isolated 3-D completely symmetric layout to minimize capacitor mismatch in the Multiplying D/AConverters (MDACs) critical to the overall ADC linearity performance, and (4) temperature- and supply-insensitive on-chip current and voltage (I/V) references using internal RC filters with optional off-chip voltage references. 2. Proposed 10 b 200 MS/s0.13µm CMOS ADC The proposed 10 b 200 MS/s ADC as illustrated in Fig. 2 employs a three-stage pipeline architecture to obtain 4 b from each stage and consists of a single input SHA, two 4 b MDACs, three 4 b sub-ranging flash ADCs, a Digital Correction Logic (DCL) block, on-chip I/V references, and onchip timing and decimator circuits. Nonlinear errors such as inter-stage offsets and clock feed-through errors in the SHA, the MDACs, and the flash ADCs are digitally corrected in the DCL by overlapping 2 b from 12 b raw codes to obtain 10 b outputs. The on-chip I/V references supply the MDACs and the flash ADCs with highly accurate and stable references, which are difficult to be implemented with off-chip references at this sampling rate of 200 MS/s. The on-chip decimator captures digital outputs of the prototype ADC at a full, a half, or a quarter conversion speed to minimize the transient noise which can be generated from the printed circuit board during measurements. 3. Circuit Implementation 3.1 Two Versions of the SHA One of the most critical circuit blocks to design low-voltage ADCs is the input sampling switch and amplifier in the SHA. The proposed wide-band low-noise SHA is implemented in two versions to maintain a 10 b resolution at 200 MS/s. The Version1 SHA, as shown in Fig. 3(a), is composed of gate-bootstrapped NMOS sampling switches [20]. The gate-bootstrapped sampling switches minimize the nonlinear distortion of sampled inputs due to switch onresistance variations depending on input signal levels by keeping the gate-source voltage of the NMOS switches constant (=V DD ) as described in Eq. (1) [21]. 1 R on = W µ n C ox L (V gs V th ), V gs V DD (1) The gate-bootstrapping circuit in a conventional CMOS ADC employs high-voltage devices with long channel and thick gate oxide in the transistors exposed to highvoltage stress to remove long-term reliability problems [12], but it requires increased chip area and clock buffers. Particularly, when high-voltage devices for input/output protection circuits in this 0.13 µm CMOS process are employed in the bootstrapping circuits, the threshold voltage is increased and the switch overdrive voltage (V gs -V th )isdecreased rapidly. As a result, the SHA cannot handle properly Nyquist-rate input signals with 10 b accuracy and shows the simulated EffectiveNumberofBits(ENOB)ofonly6b Fig. 2 Proposed 10 b 200 MS/s 0.13 µm CMOS ADC. Fig. 3 Proposed wide-band low-noise SHA. (a) Version1 with gatebootstrapped sampling switches and (b) Version2 with conventional CMOS sampling switches.

3 KIM et al.: A 10 b 200 MS/s1.8mm 2 83 mw 0.13 µm CMOS ADC BASED ON HIGHLY LINEAR INTEGRATED CAPACITORS 2039 levelat200ms/s with 1 Vp-p input signals due to a high onresistance value. The proposed SHA employs 1.2 V nominal devices with a low threshold voltage of 0.3 V to 0.4 V level and a low-parasitic capacitance in the gate-bootstrapping circuits and sampling switches. Since the 1.2 V devices may still produce the oxide failure and breakdown effects due to a high voltage exceeding a supply voltage, the Version2 SHA employs the conventional CMOS sampling switches with a sufficiently low resistance as shown in Fig. 3(b). The conventional CMOS sampling switches tend to show signal-dependent distortion in sampled input signals due to switch on-resistance variations depending on input signals as calculated in Eq. (2) [21]. The distortion degrades the dynamic performance of the SHA. The Version2 SHA reduces the distortion by employing the CMOS sampling switches with a big enough W/L ratio appropriate for the required low resistance. The simulated and measured results show that both versions of the SHA achieve the target resolution of 10 b at 200 MS/s. 1 R on = k n (V DD V tn ) (k n k p )V in k p V tp ( W ) ( W ) k n = µ n C ox, k p = µ p C ox L L n p (2) The proposed SHA is based on the conventional twocapacitor flip-around architecture to minimize power consumption and chip area at 10 b and a sampling rate of 200 MS/s. The magnitude of sampling capacitors is decided to be 0.8 pf considering the kt/c noise and the 10 b accuracy of 1 Vp-p input signals. 3.2 Highly Linear Signal-Isolated Completely Symmetric Capacitors The MDAC capacitor mismatch is one of the most critical factors to affect the ADC static and dynamic performance. The capacitor mismatch is caused primarily by random errors and systematic errors. Random errors are caused by process limitations such as inaccurate etching and oxide thickness variations while systematic errors come from different parasitic capacitances between capacitors and neighboring signal lines. As sub-micron technologies develop, random errors decrease and systematic errors can be reduced by well-defined layout techniques without additional calibration schemes [22], [23]. Three different MDAC capacitor layouts for the conventional 14 b ADCs are illustrated in Fig. 4. All unit capacitors in the Type I layout of Fig. 4(a) have a symmetrical structure and are enclosed by all the employed metals except the metals used for routing the top and bottom plates of capacitors [22]. The similar surrounding environment makes all the unit capacitors achieve high matching. The measured maximum Differential Non- Linearity (DNL) and Integral Non-Linearity (INL) of this ADC are 1.03 LSB and 5.47 LSB, respectively. Two different versions of the capacitor layout, Type II Fig. 4 Three types of the conventional MDAC capacitor layout. (a) Type I [22], (b) Type II [23], and (c) Type III [23]. and Type III, are implemented and evaluated to improve capacitor mismatch as illustrated in Figs. 4(b) and 4(c) [23]. As indicated by A in Fig. 4(b), the top metal line is not used as an interconnection line and laid out as a dummy line to reduce the capacitor mismatch caused by a parasitic fringing capacitance of the top plate. The Type II layout makes unit capacitors reside physically in the same environment as Type I. However, when signals with some different voltage levels pass through adjacent unit capacitors, each capacitor as indicated by B in Fig. 4(b) may have functionally a different parasitic capacitance. On the other hand, the Type III layout scheme of Fig. 4(c) can minimize capacitor mismatch physically as well as functionally by protecting each unit capacitor from all the passing-by signal lines. The measured maximum DNL values of two versions of the ADC are 0.77 LSB and 0.65 LSB while the maximum INL values

4 2040 IEICE TRANS. ELECTRON., VOL.E90 C, NO.10 OCTOBER 2007 Fig. 5 Proposed highly linear all signal-isolated 3-D completely symmetric capacitors. Fig. 6 Proposed on-chip current and voltage references. are 9.28 LSB and 1.80 LSB, respectively. The proposed all signal-isolated 3-D completely symmetric MDAC capacitor layout for improved linearity is shown in Fig. 5, based on the Metal-Insulator-Metal (MIM) capacitor structure using all the 8 metal lines in a 1P8M CMOS process. Since this CMOS process employs the top metal layer as an interconnection line for the top plate of capacitors, capacitor mismatch caused by parasitic fringing capacitances of the top plate cannot be reduced. On the other hand, the layout in Fig. 4(c) may have still the capacitor mismatch caused by a different interline parasitic capacitance at region C when some specific signals pass through the lines connecting the bottom plate of each unit capacitor. Capacitor mismatch can be reduced further by the proposed layout as indicated by D in Fig. 5, where additional metal lines connected to a fixed internal bias voltage are laid out between signal lines connecting the capacitor bottom plates. The proposed 4 b MDAC based on the improved capacitor layout uses the Merged-Capacitor Switching (MCS) technique [10] to reduce the number of required unit capacitors by a half. The unit capacitor sizes of the first and second MDACs are 100 ff and 60 ff, respectively, considering the required kt/c noise and the 10 b matching. 3.3 On-Chip CMOS Current and Voltage References The proposed ADC employs on-chip low-power I/V reference circuits to maintain 10 b accurate reference voltages at a sampling rate of 200 MS/s as shown in Fig. 6. The current reference block (IREF) in Fig. 6 can calibrate a current mismatch of 30% level with 3 b IVCN digital pins and the total power consumption of the ADC is reduced to 5 µw with the Power-Off (POFF) control signal set to high. On the other hand, the reference voltages connected to the ADC core tend to contain high-frequency transient glitches and switching noises due to repeated charging and discharging operations of MOS switches. In this work, simple integrated RC passive filters in the right side of Fig. 6 considerably reduce the glitches at the reference voltage outputs and minimize the settling time at a sampling rate of 200MS/s without the large off-chip decoupling capacitors of several µf level. The resistor and capacitor sizes of the RC Fig. 7 Simulated on-chip top and bottom reference voltages. passive filters are 30 Ω and 100 pf, respectively. Moreover, an inductor of 2.5 nh and a stray capacitor of 700 ff are included for this package modeling. The simulation results in Fig. 7 show that the settling times at the REFTOP and REF- BOT nodes with the on-chip RC filters alone are 0.65 ns and 0.60 ns, respectively, while the settling times of two output nodes with both of the on-chip RC filters and 0.1 µf offchip decoupling capacitors are 0.84 ns and 0.77 ns, respectively. Moreover, the voltage levels at the reference output nodes are designed to be ±0.262 V which are bigger than the ideal voltage levels of ±0.25 V by 5% considering the voltage drop due to the resistance of interconnection lines for layout. 4. Prototype ADC Measurements The proposed 10 b 200 MS/s ADC is fabricated in a 0.13 µm n-well 1P8M TSMC CMOS process. The proposed ADC has a limited number of required external pins such as inputs, outputs, and power supplies primarily for the use as a core IP block of high-performance integrated systems. The die photograph of the Version1 ADC employing gatebootstrapped sampling switches in the SHA is shown in Fig. 8(a) while the die photograph of the Version2 ADC employing CMOS sampling switches in the SHA is shown in Fig. 8(b). The actual area of gate-bootstrapped sampling switches of Version1 is µm 2 while the area of CMOS sampling switches of Version2 is µm 2. However, both versions of the prototype ADC have the same die size since other blocks than input sampling switches were designed and laid out identically for fair comparison.

5 KIM et al.: A 10 b 200 MS/s1.8mm 2 83 mw 0.13 µm CMOS ADC BASED ON HIGHLY LINEAR INTEGRATED CAPACITORS 2041 Table 1 ADCs. Performance comparison of the recently published 10 b CMOS Fig. 8 Die photograph of the prototype ADCs. (a) Version1 with gatebootstrapped sampling switches and (b) Version2 with conventional CMOS sampling switches (both 1.32 mm 1.36 mm). Fig. 10 Signal spectrum of the Version2 ADC measured with a 10 MHz sinusoidal input at 200 MS/s (data1/4 fs down-sampled). Fig. 9 Measured DNL and INL of the Version2 ADC based on conventional CMOS sampling switches. The functional blocks encircled by the bold continuous and dotted lines in Fig. 8 represent the PMOS and NMOS onchip decoupling capacitors, respectively. The on-chip decoupling capacitance of 300 pf level is needed to stabilize the top and bottom reference voltages and the internal signal common voltage while the on-chip decoupling capacitance of 180 pf is integrated on the idle space of the ADC to reduce glitches from analog and digital power supplies. The prototype ADC occupies an active die area of 1.8 mm 2 (=1.32 mm 1.36 mm) and dissipates 83 mw at 1.2 V and 200 MS/s. The measured DNL and INL of the Version1 prototype ADC employing gate-bootstrapped sampling switches are within 0.38 LSB and 0.48 LSB. The Version2 ADC employing CMOS sampling switches in the SHA shows the maximum DNL and INL of 0.24 LSB and 0.35 LSB as illustrated in Fig. 9. From the standpoint of static linearity performance, the Version2 ADC employing CMOS sampling switches is a little bit better than the Version1 ADC. Table 1 summarizes the performance comparison of the proposed ADC and the recently published pipeline CMOS ADCs with a 10 b resolution and hundreds of MS/s. As shown in Table 1, the proposed ADC demonstrates almost the best static linearity performance of DNL and INL based on the proposed all signal-isolated 3-D completely symmetric capacitor layout. The figure of Merits (FOM), defined as Power/(2 ENOB Fs), is 1.01 pj/conversion-step at a 10 MHz input with 200 MS/s. The typical signal spectrum of the Version2 prototype ADC employing CMOS sampling switches is measured with a 10 MHz input frequency at a sampling rate of 200 MS/s as plotted in Fig. 10. Digital output data are captured at a quarter rate of the full conversion speed of 200 MHz by the on-chip decimator to minimize digital coupling noise. The measured dynamic performance of the prototype ADCs is summarized in Fig. 11. The Signal-to-Noiseand-Distortion Ratio (SNDR) and Spurious-Free Dynamic Range (SFDR) of the Version2 ADC employing CMOS sampling switches in Fig. 11(a) are measured with different sampling rates up to 250 MS/s ata10mhzdifferential input. The SNDR and SFDR are maintained over 54 db and67dbuptoasamplingrateof200ms/s. With a maximum sampling rate of 250 MS/s, both of the SNDR and SFDR are maintained above 48 db and 61 db which are reduced by 6 db compared to a 200 MS/s sampling rate. The SNDR and SFDR of the Version2 ADC employing gatebootstrapped sampling switches in Fig. 11(b) are measured with increasing input frequencies at the sampling rates of 200 MS/s and 250 MS/s. With input frequencies increased to

6 2042 IEICE TRANS. ELECTRON., VOL.E90 C, NO.10 OCTOBER 2007 Fig. 11 Measured dynamic performance of the prototype ADCs: SFDR and SNDR versus (a) fs (with Version2 ADC) and (b) fin (with Version1 ADC). Table 2 Performance summary of the prototype ADCs. This work proposes a 10 b 200 MS/s 1.8mm 2 83 mw 0.13 µm CMOS ADC for high-quality video system applications such as next-generation DTV, radar vision, and wireless communication systems such as WLAN, WiMax, SDR, LMDS, and MMDS. The following circuit design and layout techniques are considered to obtain the required target performance. First, the proposed ADC employs a three-stage pipeline architecture to optimize resolution and low power dissipation at 200 MS/s. Second, the wide-band low-noise input SHA employs two versions of input sampling switches, gate-bootstrapped switches and CMOS switches, for performance verification and comparison. As both versions of the SHA show 10 b input accuracy with similar static and dynamic performance at 200 MS/s, the ADC version based on CMOS switches occupying smaller area may be more efficientin this levelof 10band200MS/s. Third, the improved all signal-isolated 3-D completely symmetric layout technique is proposed in two MDACs to minimize capacitor mismatch by isolating each unit capacitor from all neighboring signal lines with all the employed metal lines and by placing extra internal metal lines between signal lines connecting the bottom plate of each unit capacitor. In addition, the ADC has on-chip low-power I/V references with optional off-chip voltage references. The on-chip PMOS and NMOS decoupling capacitance of 500 pf level is integrated to minimize coupling noise. The prototype ADC in a 0.13 µm 1P8MCMOSprocess shows the measured DNL and INL within 0.24 LSB and 0.35 LSB while the ADC shows a maximum SNDR of 54 db and 48 db and a maximum SFDR of 67 db and 61 db at 200 MS/s and 250 MS/s, respectively. The ADC occupies an active die area of 1.8 mm 2 and consumes 83 mw at 200 MS/s and a 1.2 V supply. Acknowledgements This work was partly supported by the Nano IP/SoC Promotion Group of Seoul R&BD Program 2006, the System 2010 Project, and the IDEC of KAIST. References the Nyquist frequency, the SNDR and SFDR are maintained above 50 db and 63 db at 200 MS/s and above 43 db and 56 db at 250 MS/s, respectively. Both of the two Versions of the prototype ADC show the similar dynamic performance. The measured performance of the prototype ADCs is summarized in Table Conclusion [1] B. Vaz, J. Goes, and N. Paulino, A 1.5-V 10-b 50 MS/s timeinterleaved switched-opamp pipeline CMOS ADC with high energy efficiency, Symp. VLSI Circuits Dig. Tech. Papers, pp , June [2] S.T. Ryu, B.S. Song, and K. Bacrania, A 10 b 50 MS/s pipelined ADC with opamp current reuse, ISSCC Dig. Tech. Papers, pp , Feb [3] H.C. Choi, J.H. Kim, S.M. Yoo, K.J. Lee, T.H. Oh, M.J. Seo, and J.W. Kim, A 15 mw 0.2 mm 2 10 b 50 MS/s ADC with wide input range, ISSCC Dig. Tech. Papers, pp , Feb [4] Y.I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, A low-power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply, Proc. IEEE Int. Symp. Circuits and Systems, pp , May [5] B.M.Min,P.Kim,D.Boisvert,andA.Aude, A69mW10b 80 MS/s pipelined CMOS ADC, ISSCC Dig. Tech. Papers, pp , Feb [6] O. Stroeble, V. Dias, and C. Schwoerer, An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection, ISSCC Dig. Tech. Papers, pp , Feb [7] Y.I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 V power supply, ISSCC Dig. Tech. Papers, pp , Feb

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