IMPLEMENTING THE 10-BIT, 50MS/SEC PIPELINED ADC

Transcription

1 98 CHAPTER 5 IMPLEMENTING THE 0-BIT, 50MS/SEC PIPELINED ADC

2 INTRODUCTION This chapter is devoted to describe the implementation of a 0-bit, 50MS/sec pipelined ADC with different stage resolutions using the designed blocks of chapter. An N-bit pipelined ADC can be implemented in any number of stages. If only a single bit is converted per stage then, we need 0 stages. However, if two bits are converted per stage then, only five stages are required and so on. This chapter discusses about the implementation of 0-bit pipelined ADCs with,.5,, 3, and 5-bits/stage conversion mechanisms. 5. -BIT /STAGE PIPELINED ADC An N-bit pipelined ADC can be implemented in any number of steps. If only a single bit is converted per stage, then we need N stages connected in series as shown in Fig. 5.. This ADC can achieve high resolution and at high speeds [5].

3 00 Fig. 5. One bit/stage Pipelined ADC As shown in Fig. 5., each stage is called a multiplying DAC (MDAC), consisting of a -bit sub-converter (comparator), a S/H amplifier, a subtractor and a residue amplifier with a gain of two. The operation of the circuit is as follows.. The input signal is sampled and compared with /. If in > / the output of comparator is. If in < /, the output of comparator is 0. The comparator output is the converted bit of that stage.. If in > /, then comparator output= and / must be subtracted from the input signal and the residue is passed to the amplifier with a gain of two. However if in < /, then the output of comparator = 0 and 0 must be subtracted from the held input and the residue is passed to amplifier for providing a gain of two i.e., If in >, output of residue amplifier is in- and If in <, output of residue amplifier is in.

4 0 The output of residue amplifier becomes the input to the next stage S/H circuit and the process repeats until the signal passes through all the stages. Here, all the odd numbers stages operates on Φ while all the even number stages operates on Φ so that, when even stages samples on the residues of odd stages, the odd stages are free to sample the output of even stages. Since all stages are processing simultaneously, the pipelined ADC results in a high throughput. After an initial delay of N-clock cycles called latency, one conversion will be completed per clock cycle. 5.. Switched capacitor MDAC (unipolar input) The structure of MDAC to convert -bit/stage can be implemented using switched capacitor circuits. The circuit for unipolar input is shown in Fig. 5.. The switch connections shown are for the MDAC in sampling mode. During sampling, the capacitor Ci and Cf are charged to in. During hold mode, the switches S to S3 change their positions.

5 0 Fig. 5. Single bit MDAC for Unipolar input Now C i is connected to the DAC output and C f is connected in the feedback path of op-amp to work as a difference amplifier. For -bit/stage conversion, the sub ADC simply reduces to a single comparator. The comparator compares the hold input signal with /. If in > /, the output of comparator, D= and if in < /, the output of D= 0. When D= the D/A converter switch connects + to C i else if D = 0, ground is connected to C i. Theore the op-amp along with C i and C f acts as a residue amplifier. The expression for the output of amplifier is C = Eq. (5.) i residueout in D. C f If Ci = Cf, then residueout = in- for D= and residueout = in for D= 0 as required. The output of this MDAC is fed as input to the next stage and so on.

6 Switched capacitor MDAC (bipolar input) The MDAC circuit for bipolar input i.e., in between and + is as shown in Fig Fig. 5.3 Single bit MDAC for Bipolar input The output of this MDAC can be expressed as C = Eq. (5.) i residueout in + D. C f Here D can be ±. Theore for C i = C f the output can be residueout = in+ for D=+ And residueout = in- for D=- The gain accuracy of this converter depends on the matching accuracy of the capacitor C i and C f. Although, single ended op-amp architecture is used here; we can extend this for differential op-amp architecture

7 0 as shown in Fig. 5. so that the noise and offsets and other errors are minimized. Fig. 5. Fully Differential S/H circuit with gain The expression for residue output now modifies to out C i C = i outp outn = + ( inp inn ) ( DACP DACN ) -----Eq. (5.3) C f C f In this architecture, the first stage output (MSB) is available much earlier than the outputs of other stages. Theore, we need to synchronize the outputs by making them move through a series of latches/flip-flops. The waveforms of Fig. 5.5 shows the various lengths of shift registers required for different stages. From figure it is clear that the first stage output must be passed through five positive edge triggered flip-flops and one negative edge triggered flip-flop and the

8 05 last stage needs only one positive edge triggered flip-flop. The latency of this converter is seen to be 5 clock cycles. Fig. 5.5 Waveforms to decide the shift logic of different stages 5..3 Accuracy issues of -bit/stage pipelined ADC Assume all the components to be ideal. The one bit/stage ADC can be analyzed by estimating the switching voltage of the comparators for the ideal and the non-ideal cases. Let SW be the input voltage at which the first stage comparator switches. Theore, SW = ½ -----Eq. (5.) The input voltage on the second comparator will then be i = in DN Eq. (5.5)

9 06 Where, D N- is the MSB output of first stage comparator. The second stage comparator now switches when i = ½. Theore, SW = D N Eq. (5.6) Proceeding like this, we can write the input voltage to the third stage comparator as i3 = ( in DN. ) ( DN. ) -----Eq. (5.7) and the switching voltage of third comparator is SW3 = D N-. D N-. + The general expression can now be written as Eq. (5.8) 8 SWN = DN-. + DN-. + DN D. + N- N -----Eq. (5.9) 8 D 0 will not be seen in above equation as no more conversion is required after the last stage. Now let us evaluate the switching voltages for comparator for the non-ideal cases. Let us include the S/H amplifier offset voltage ( SHO) and comparator offset ( CO) as the non-idealities. Let all the residue amplifiers have equal gain A. The input voltage to the non-ideal comparator of the first stage is ' i in + = -----Eq. (5.0) SHO Then the switching voltage of this comparator will be ' SW Equating Eq. (5.0) and Eq. (5.), we get = + CO -----Eq. (5.)

10 07 ' SW = Eq. (5.) CO SHO The input voltage to the non-ideal second stage comparator will be = -----Eq. (5.3) ' i ( in + SHO DN. ). A + SHO Then the switching voltage of second stage comparator will be ' SW = DN. + SHO ( SHO CO ) -----Eq. (5.) A A Extending this to the last stage, we can generalize the switching voltage of the N th stage as ' SWN = D N. + D N D A A N + A N + A CON N N k= SHOK K A ----Eq. (5.5) The integral non-linearity (INL) error of one bit pipeline stage can be evaluated by subtracting the switching voltages of non-ideal and ideal cases. The INL of first stage can be written by subtracting SW from SW. i.e., INL = = -----Eq. (5.6) ' SW SW CO SHO Similarly INL ' SHO CO = SW SW = SHO Eq. (5.7) A A A And --Eq. (5.8)

11 08 The addition of all offsets must be within ½ LSB for the ADC to be accurate. In equation for INL N, we see that the effect of offsets on INL of N th stage is minimal as it is divided by a large gain. Theore, the later stages of a pipelined ADC are more accurate and the design is not a critical issue. Hence, by using less accurate designs for the last stages, we infact can save area and power. The last term of Eq. (5.8) indicates that the effect of first stage on INL is the largest. Theore, in pipelined ADC design, the first stage must be much more accurate than the later stages. Hence, the first stage is designed caully and later stages designed only to save area and power. The differential non-linearity error (DNL) can be evaluated by calculating the worst case difference of the switching points and then subtracting the ideal value of an LSB. The worst case switching occurs when digital output switches from 0. to when all bit positions are changed. Theore, DNL max ' ' = SW SWN -----Eq. (5.9) N By substituting D N- = and all other bits = 0 in the expression for SWN, We get DNL max N N = CON + K CO + N K = A A K = SHOK K A N -----Eq. (5.0) This value must be less than ½ LSB BITs /STAGE PIPELINED ADC

12 09 In ADC/DAC, one bit corresponds to two levels, 0 and and two bits corresponds to four levels 00, 0, 0 and. In a stage, if we use only three levels for conversion then it is.5-bits/stage conversion. Fig. 5.6 Sub-converter Architecture for Unipolar input A.5-bits/stage is a -bit/stage into which we add some redundancy to compensate for the device imperfections and tolerances. The digital error correction algorithm [6] removes this redundancy at a later stage to convert the output back to -bit. The sub-converter architecture for.5 bit/stage with unipolar input is as shown in Fig. 5.6 and for the bipolar input the figure is as shown in Fig. 5.7.

13 0 Fig. 5.7 Subconverter Architecture for Bipolar input The Fig. 5.8 shows the transfer characteristics for single ended and bipolar input signals. For unipolar signals, if in < then the digital output will be ab = 00 and if 3 < in < then the digital output will be ab = 0 and if 3 in > then the digital output will be ab =. And for bipolar input, if in < then the digital output will be ab = 00 and if < + in < then the digital output will be ab = 0 if in + > then the digital output will be ab =.

14 (a) (b) Fig. 5.8 Transfer curves for (a) unipolar and (b) Bipolar inputs The encoding logic changes to 0. So that the output of analog multiplexer (DAC) will be as shown in Table 5. Table 5. Generation of codes in sub-converter Input range ab Output of DAC Output of MDAC in < 00 - in+ < + in < 0 0 in in + > 0 + in- 5.. MDAC implementing.5-bits/stage The MDAC circuit with single ended output used to implement this table is as shown in Fig During sampling mode, S is closed and S is open to sample the input signal onto the capacitors Ci and Cf.

15 During the hold mode, the switches change their positions. Now the sub ADC and DAC connects ( /0/- ) to C i and the capacitor C f will be in feedback path of the op-amp. The output of MDAC will then be as shown in Table 5.. Fig bit MDAC 5.. The redundancy bit removal algorithm This algorithm converts the bit code of a stage to the final -bit/stage code. The expected error sources in pipelined ADCs are offset voltages of amplifiers and comparators, gain errors in amplifiers and also the non-linearity errors in sub-converters. Many of these errors can be corrected by using the.5-bits conversion and this algorithm. To generate the final code, the individual bits of all stages must be added in a predetermined way as follows. If DN-, is the MSB

16 3 bit of N th stage and D N-,0 is the LSB bit of N th stage and so on. Then output code is achieved by adding them as shown below. D N-, D N-,0 D N-, D N-,0 D N-3, D N-3, D, D,0 D 0, D 0,0 D N- D N D D D 0 To achieve this, we need to use a combination adder with inputs as shown in Fig Fig. 5.0 Digital Arithmetic in.5-bits/stage Table 5. shows the conversion mechanism and the codes generated in a three stage pipeline. For example, if in = 0.79, then the codes generated by successive stages will be (as shown highlighted in third row) 0, 0, and 00.

17 Table 5. Code generation in subconverters of.5bits/stage These codes must be added in a predetermined way as follows. Discarding the LSB, the final output code for in = 0.79 is 0. The same logic is extended to generate a 0-bit error corrected output code BITs /STAGE PIPELINED ADC The detailed block diagram of a -bits/stage pipelined ADC is shown in Fig. 5.. We need 5 stages to implement a 0-bit pipelined

18 5 ADC. Each stage generates -bits which are passed through a chain of shift registers of varied lengths. Fig Bit Pipelined ADC with -bits/stage The waveforms of Fig. 5. shows that stage one needs three positive edge triggered flip flops to shift data while stage two requires two positive edge triggered flip flops and one negative edge triggered flip flop and so on.

19 6 Fig. 5. Waveforms to decide shift register lengths Each stage in the pipeline has a -bit flash sub-converter, encoding logic, DAC and a switched capacitor amplifier with gain of as shown in Fig Fig. 5.3 Stage details of -bits/stage pipelined ADC

20 7 The code conversion mechanism is explained in Table 5.3. Table 5.3 Code generation in subconverter of -bits/stage in Code Output of DAC Output of stage in < 00 0 in < in < 0 in 3 < in < 0 in 3 3 in > 3 in 5.3. Two bit priority encoder The output of comparator blocks (abc) and the required digital output code generation is shown in Table 5.. The priority encoder design is based on the inputs(abc) and outputs(b B0) of the table. Table 5. Truth table of 3: priority encoder

21 8 From Table 5., using sum of products we get B = bc B0 = a b c+abc And the CMOS digital implementation is shown in Fig. 5.. Fig. 5. Two Bit Priority Encoder 5.3. Two bit DAC The circuit diagram for -bit DAC is shown in Fig The DAC is implemented using transmission gates only. As the DAC doesn t use an op-amp, it is inherently fast. The input and output details of DAC are shown in Table 5.3. The simulation results of -bit D/A Converter is shown in Fig The delay of the DAC is seen to be ns. The latency of this ADC is 3 clock cycles.

22 9 Fig. 5.5 Two bit D/A Converter Fig. 5.6 Simulation results of -bit D/A Converter

23 BITs /STAGE PIPELINED ADC Using 3-bits/stage, we need at least four stages as shown in Fig. 5.7 with the first three stages converting 3-bits/stage and the last one converting -bit. Fig Bit Pipelined ADC with 3-bits/stage The sub-converter uses a 3-bit flash subconverter and a 3-bit priority encoder to generate the final 3-bit code/stage. The 3-bit DAC implemented is an R-R ladder DAC as shown in Fig This architecture needs four S/H amplifiers and comparators. The simulation results of 3-bit R-R DAC are shown in Fig. 5.9 and the delay of the 3-bit DAC is seen to be.5ns.

24 Fig bit D/A Converter Fig. 5.9 Simulation results of 3-bit D/A Converter

25 Fig Bit flash subconverter and encoding logic bit priority encoder The requirements of 3-bit priority encoder are as shown in Table 5.5. The outputs of comparators (X 7 to X ) are the inputs to the priority encoder. The inputs are transformed to (a7 to a0) by using XOR logic. Starting from LSB bit and XORing the adjacent bits in every row, we get results (a7 to a0) as shown in Table 5.5. Using SOP, the Boolean expression for the final digital output (BBB0) can be evaluated as follows B0 = a+a3+a5+a7 B = a+a3+a6+a7 B = a+a5+a6+a7

26 3 Input Range Table 5.5 Encoding logic in 3-bits/stage Comparator outputs (X 7 to X ) Inputs after XORing (a 7 to a 0) Digital Outputs (B B B 0) in < > in > > in > > in > > in > > in > > in > in > Theore, to implement a 7:3 priority encoder we need seven twoinput XOR gates and three four-input OR gates. The final digital circuit of 3-bit priority encoder is as shown in Fig The XOR and OR gates are implemented in fully static CMOS logic with minimum transistor sizes to save area and power. The digital output (B B B 0) is passed through a bank of shift registers to result in the final digital output. The waveforms and the number of flip flops required in every

27 stage is shown in Fig. 5.. The latency for this ADC is only ½ clock cycles. Fig. 5. Waveforms deciding shift register lengths in different stages 5.5 -BITs /STAGE PIPELINED ADC Using -bits/stage, we need at least three stages with first and second stage converting -bits each and the third stage -bits. The general block diagram is shown in Fig. 5.. Fig bit Pipelined ADC with -bits/stage

28 5 The first two stages in the pipeline have -bit flash sub-converters and the third has a -bit flash. Each stage has encoding logic and a DAC. This architecture needs only three S/H amplifiers with gains of 6, 6 and. This ADC needs 33 comparators to implement the subconverters. A 5: priority encoder is required here. It is implemented using the extended logic as discussed for -bit priority encoder. The final Boolean equations to be implemented are B 0 = a +a 3+a 5+a 7+a 9+a +a 3+a 5 B = a +a 3+a 6+a 7+a 0+a +a +a 5 B = a +a 5+a 6+a 7+a +a 3+a +a 5 and B3 = a8+a9+a0+a+a+a3+a+a5 The DAC is a -bit R-R ladder DAC for stages with -bits conversion and for the -bit last stage, the DAC uses of simple set of transmission gates. The S/H amplifier circuit used is switched capacitor type discussed previously. The S/H amplifier of the first two stages needs a gain of 6. Hence C i/c f is appropriately adjusted to result in the required gain. The waveforms explaining the digital shift logic are shown in Fig The latency for this -bits/stage pipelined ADC is only two cycles.

29 6 Fig. 5.3 Waveforms to decide shift register length in different stages The -bit DAC implemented is an R-R ladder DAC as shown in Fig. 5.. The simulation results are shown in Fig Fig. 5. Schematic of -bit D/A Converter

30 7 Fig. 5.5 Simulation results of -bit D/A Converter BITs /STAGE PIPELINED ADC Using 5-bits/stage, this pipelined ADC needs only two stages. The general block diagram is as shown in Fig Fig bit Pipelined ADC with 5-bits/stage

31 8 The waveforms shows that the first stage needs two flip-flops, a positive edge triggered flip-flop followed by a negative edge triggered flip-flop. However, stage two needs only one positive edge triggered flip flop. The latency for this ADC is only ½ clock cycles. Since there are only two stages, this ADC needs only two S/H amplifiers. The two subconverters use 5-bit flash stage and hence needs 6 comparators. The subconverters generate 3 outputs which are to be finally converted to 5-bits. Theore, we need a 3:5 bit priority encoder and is implemented using the extended logic of -bit priority encoder. 5.7 LAYOUT ISSUES OF PIPELINED ADCs A fixed height layout, with variable widths is always perred in CMOS design. It is also perred to have analog signals and digital signals separate. Fig. 5.7 Layout structure with fixed height Fig. 5.7 shows a typical layout structure with fixed height. DD and SS lines are wide enough and also separated by enough distance to

32 9 accommodate PMOS transistors close to DD and NMOS transistors towards SS. A typical pipelined ADC has switched capacitor S/H amplifier, comparators and clock generator circuits as analog blocks and digital storage, shifting and error correction circuits as digital blocks. These analog and digital blocks may be separated as shown in Fig. 5.8 [7] [8]. The following points must be looked into when laying out the design.. Let the differential input signals be laid out close to each other as shown in Fig So that the noise that interferes (common mode signal) will be equal on both lines and hence cancels out. Let all the differential signals be laid out like this.. Let the input signals be surrounded by ground pads as shown. This reduces the noise coupling onto the input signals. 3. At high sampling rates, clock signals also radiate a lot of energy. Hence let the clock signal also be surrounded by ground pads so that it will not interfere with differential input signals.. More number of DD and SS pads may be used in analog circuits so that the supply to op-amps and the erence voltages are separated. 5. Outside the chip, both analog and digital DD and SS can be common. But, within the chip they must be separated as shown. 6. Decoupling capacitors can be used separately for analog and digital as shown in Fig. 5.9.

33 30 Fig. 5.8 Block Layout of a Pipelined ADC 7. Power and ground wires must be as wide as possible to handle the required currents. Low noise signals can be routed in the space between the op-amps. 8. Use guard rings, around sensitive analog circuits. This can avoid coupling of substrate noise. 9. If a digital signal is moving over a sensitive analog signal or viceversa, shielding must be provided. For example, if sensitive analog signal is on metal and the digital signal is on metal3, then analog ground in M layer is interposed between M3 and M layers. This shielding provides isolation between the analog and digital signals.

34 3 Fig. 5.9 Decoupling capacitors in mixed signal chip 5.8 SPECIFICATIONS OF IMPLEMENTED ADC The specifications of implemented bit/stage ADC are listed in Table 5.6. The FFT plots for MHz and 0MHz inputs are as shown in Fig The INL and DNL curves are shown in Fig Table 5.6 Specifications of Implemented ADC Technology 0.8μm Resolution 0 Bits Conversion Rate 50MS/sec Supply oltage 3.3 Power Consumption 0mW SNDR 56.9dB at input frequency of MHz 5.6dB at input frequency of 0 MHz SFDR 69dB ENOB 8.8b INL ± 0. LSB DNL ± 0. LSB Transistor Area 960μm Temperature Range 0 to 80 o C

35 3 Fig FFT of MHz and 0MHz tones sampled at 50MHz Fig. 5.3 Measured INL and DNL