IES Digital Mock Test

Transcription

1 . The circuit given below work as IES Digital Mock Test - 4 Logic A B C x y z (a) Binary to Gray code converter (c) Binary to ECESS- converter (b) Gray code to Binary converter (d) ECESS- To Gray code converter. In the circuit given below, the output f as a function of x, y is x y 4 decoder 4: MU S (MSB) S f y x (a) NOR (b) NAND (c) OR (d) NOR. and are bit binary number 4: MU S S f 4: MU S S f y x x y The output f f of the above circuit represents (a) sum output of bit addition (b) carry output of bit addition (c) borrow output bit subtraction (d) none of the above

2 4. The state diagram for the circuit below is T T-FF Clk (a) x = x = x = x = x = (b) x = x = x = (c) x = x = (d) x = x = x = x = x = x = 5. What is the output voltage of the D/A converter after applying 4 clock pulses. Assume the Johnson counter is initialized to. The input-output table of digital to analog converter is given below. Clk bit Johnson counter D/A converter V =? D/A Converter Digital Input Analog Output V V V V 4 V 5 V 6 V 7 V (a) V (b) V (c) 5 V (d) 7 V

3 6. ` Clk T T T The Synchronous circuit shown above works as (a) up counter if = (b) up counter if = (c) down counter if = (d) down counter if = 7. The TTL circuit shown below works as C TTL Totempole NAND A B TTL Totempole NAND TTL Totempole NAND TTL Totempole NAND y (a) Decoder (b) Multiplexer (c) Demultiplexer (d) None 8. Minimum number of input NAND gates required to implement the Boolean Expression A B C (a) 7 (b) 8 (c) 9 (d) none 9. For a TTL circuit I OH = 4 A, I IH = 4 A, I OL = 6 ma, I IL = ma. The Fanout is 8 (a) (b) 8 (c) (d) None

4 . V a Analog Input Successive Approximation ADC Clk Digital Output The 4 bit successive approximation ADC has full scale value of 5V. the sequence of states is shown below. The analog input lies in the range. Start END (a) 8 V 9 V (b) 9 V V (c) V V (d) can t be determined. For the 4 bit DAC shown below, the Analog output voltage is (Assume ideal OP-Amp) V k k k k k k k k k _ +5V + -5V V (a).875 V (b).75 V (c) 5 V (d) 5 V. Integrated output waveform for the dual scope ADC is shown in the figure. The time T for on 8 bit counter with 4 MHz clock will be V T t

5 (a). ms (b).64 ms (c).64 ms (d).4 ms. What is the equivalent Boolean Expression in product of sums form for the K-Map in the figure. Ans: (c) (a) B C D B C D (b) B D B D (c) B D B D (d) None 4. The result of (45) (45) 6 expressed in s complement representation is (a) (b) (c) (d) Ans: (c) 5. AB CD b b b b 4 bit Binary Adder d 4 d d d b Consider the above circuit. It has 4 bit binary input b b b b and has the five bit output d 4 d d d d. The circuit implements. (a) Binary to Hex conversion (c) Binary to excess- conversion (b) Binary to BCD conversion (d) Binary to radix conversion

6 6. Consider the following statements. Taking two s complement is equivalent to sign change. For a 4 bit number A, A+ one s complement A is equal to 4.. Fan in of a gate is always equal to Fan out of the same gate. 4. Master Slave Flip Flop stores bits of data. Which of the following is true. (a) only (b) and (c),, only (d),,, 4 only 7. is a signed integer. The s complement representation of is (F87B) 6. The s complement representation of 8 * P is where * represents multiplication (a) (CD8) 6 (b) (87B) 6 (c) (F878) 6 (d) None of the above 8. Assertion: It is not desirable to drive transistor into hard saturation for high speed switching circuits. Reason: It is difficult to bring back transistor to cutoff from hard saturation. 9. In the given circuit if clock frequency is MHz, then frequency fout is CLK C D B D A C B A f out CLR CLR CLR 4: MU S (MSB) S C A B (a) 5 KHz (b) 5 KHz (c) MHz (d) None Ans: (c). Assertion: The speed of DRAM is faster than processor. Reason: Bit is stored as charge in DRAM.

7 . The simultaneous equations of Boolean variables W,,, Z are + + Z = = W Z Z W The value of W,,, Z are (a) (b) (c) (d) none Ans:. Match List I with List II & select the correct answer using the code given below. List I List - II P.. : MU S : MU S R : MU S Code: P R (a) (b) (c) (d)

8 . Assertion: Switching speed of ECL Logic family is high as compared TTL. Reason: Transistors with high storage times are used in ECL logic family. Ans: (c) 4. An 8 bit digital to analog converter has full scale output voltage of V and an accuracy of.%. The maximum error for any output voltage will be (a) mv (b) mv (c) /55 mv (d) None 5. Assertion: Carry look ahead adder is faster than ripple carry adder. Reason: Carry look ahead adder generates carry bits directly from input. 6. Consider the following statements.. PROM contains programmable AND array and programmable OR array.. PLA contains fixed AND array and programmable OR array.. Minimum number of MOSFET s required for bit DRAM cell is BCD, 4 & ECESS are self complementing codes. Which of the following is correct (a) and 4 only (b) and 4 only (c),,, 4 (d) none of the above 7. Assertion: MOS logic family has higher fanout as compared to RTL. Reason: Noise margin of MOS logic family is higher compared to RTL. 8. Consider the following statements. Registers are made of edge triggered flops where as latches are made from level triggered flip flops.. Latch employs cross coupled feed back connections.. Noise immunity is the amount of noise which can be applied at the input of the gate without causing the gate to change state. 4. Propagation delay is the time required for a gate to change its state. Which of the following statements are NOT correct. (a) and (b) and 4 (c),,, 4 (d) none

9 9. In the TTL totempole inverter given below if input V i =.7V then V CC = 5V 4k.4 k k 4 V i =.7V D V k k Match the transistors and their operating regions List I List - II P.. Active.. Saturation R.. Cutoff S Reverse Active Codes: P R S (a) 4 (b) (c) (d) 4. Assertion: The Dual slope integrating type ADC is slow compared to other converters. Reason: The conversion time is different for different analog input voltages.