Implementing a 5-bit Folding and Interpolating Analog to Digital Converter

Transcription

1 Implementing a 5-bit Folding and Interpolating Analog to Digital Converter Zachary A Pfeffer (pfefferz@colorado.edu) Department of Electrical and Computer Engineering University of Colorado, Boulder CO Abstract In this paper I describe an implementation of a 5-bit folding and interpolating analog to digital converter (FI-ADC). A FI-ADC is used to perform analog to digital conversions in as few clock cycles as possible. The implemented FI-ADC was a major block in a larger chip. The larger chip provided analog to digital (ADC) and digital to analog (DAC) capabilities for a PC parallel port configured in standard parallel port (SPP) mode. The chip was not fabricated. The chip was designed in a 0.35 um CMOS process from Austriamicrosystems. It was designed, simulated and laid out with Cadence design tools, specifically: IC (custom IC design), LDV 3.4 (digital design & verification), SPR 4.0 (digital synthesis) and Virtuoso XL (layout). A post layout simulation was not performed. The specifications for the 5 bit FI-ADC were: an input range of 0 to 1.8 V (Vref), a conversion rate of 2 million samples per sec, a 200 khz bandwidth on the input and less than 1 least significant bit (LSB) for the integral non-linearity (INL) and differential non-linearity (DNL). All specifications were met or exceeded. The maximum INL was 0.62 and the maximum DNL was The sampling rate could be set as high as 3 million samples per second and signals with frequency components of up to 200 khz were passed through simulation without significant distortion. 1. Introduction A FI-ADC is considered a high-speed ADC architecture. Ideally, it performs one analog conversion every clock cycle. At the core of the FI-ADC is a folding and interpolating circuit and a coarse ADC which decodes the folding and interpolating circuit's output. The FI-ADC architecture was built to solve limitations in straight flash ADC's, specifically the number of comparators and the need to balance electrical delays. A simple flash ADC needs 2 N -1 comparators and the electrical delay of getting to and through each comparator must be kept the same. Interpolation reduces the number of comparators. Folding also reduces the number of comparators and allows each comparator to operate in the same subrange. By combining folding and interpolating, the output comparators only needed to resolve zero crossings and a coarse range of input voltages. A coarse circuit is used to decode each fold. For instance, using a 2 bit coarse ADC the input can be folded 4 times. The coarse ADC is used by the post-folding circuit interface to correlate the folder's output with which fold the output came from. It is typically implemented using a standard flash ADC scheme that tries to balance its delay with the folder's delay. In a 4 fold circuit one input of each amplifier is connected to 1*LSB, 9*LSB, 17*LSB and 25*LSB. The other input of each differential amp is connected to the input voltage.

2 Figure 1. The folding circuit. As the input voltage rises the differential output swings from the same maximum to the same minimum 4 times. As the input voltage passes each LSB set point the differential output voltage passes through zero. The folding circuit is implemented by parallel connected differential amplifiers. One input of each amplifier is connected to a voltage at a LSB multiple. For instance, a 2 bit coarse ADC requires a folder with 4 parallel connected differential amplifiers to fold the input 4 times. A circuit diagram is given in Figure 1. The parallel differential amps implement a continuous triangle wave fold. A circuit to generate a discontinuous saw-tooth wave can also be built. Interpolation can be implemented by arraying a folding circuit. For a 3 bit interpolation scheme each input of each differential folding circuit is set to (1+i) *LSB, (9+i)*LSB, (17+i)*LSB and (25+i) *LSB where i runs from 1 to 8. This puts each differential output of the arrayed folding circuit at a zero crossing for all LSB multiples in the entire input range as shown in figure 2. Some other high-speed ADC architectures are multiple-bit pipeline and timeinterleaved. Figure 2 The ramp is the input voltage. The eight folds of the differential output are shown below it. 2. Implementation The implemented FI-ADC contained 6 main sub-blocks, the folding and interpolating circuit, the FI-ADC and coarse ADC comparators, the sample-andhold circuit, the coarse ADC, the digital decoder and a clock divider circuit to

3 interface the FI-ADC to the chip's 40 MHz clock. 2.1 The Folding and Interpolating Circuit The folding and interpolating circuit consisted of 8 folders. Each folder contained 4 differential amplifiers connected in parallel. Each folder used 2 large bias poly resistors for their loads and tapped each LSB from 4, 32 element poly resistor chains. 2.2 The FI-ADC and Coarse ADC Comparators In order to save time the FI-ADC and coarse ADC used the same comparators. The comparators were implemented using a standard non-compensated two-stage architecture. They could sustain 3 million samples per sec, were the slowest part of the chip and had a 30 mv offset; below one LSB (56 mv). 2.3 The Sample-and-Hold Circuit The initial FI-ADC design did not use a sample and hold circuit. One was added to stabilize the input. Introducing one required the single phase clock to be split into a nonoverlapping two phase clock. The sampleand-hold circuit used a folded and cascoded single stage amplifier in a unity gain configuration, preceded by a NMOS switch and a 1 pf poly capacitor. The cascoded single stage amplifier was run with a very low bias current and large output FETs. This was done to obtain nearly rail to rail operation at its output. A full range output was important because the circuit needed to be able to operate with ouput values below 1 LSB to resolve 5'b00000 correctly. The coarse ADC was implemented using a flash ADC architecture. It used 3 comparators and 4 poly resistors to resolve 1/4 Vref, 1/2 Vref and 3/4 Vref. Since a sample-and-hold was used the coarse ADC's delay did not need to match the folding circuit's delay. 2.5 The Digital Decoder The digital decoder took the output from the 8 folding circuit's and coarse ADC's comparators and produced a binary encoded 5-bit value. The circuit was written in Verilog and synthesized as a combinational block with output flops to capture the output word on the rising edge of the second clock phase. 2.6 The Clock Divider Circuit The FI-ADC was half of the main circuit. The other half, a 5-bit charge redistribution DAC, used multiple clock cycles to compute its result. As a result, the ADC divided down the 40 MHz clock to 2 MHz. The circuit was written in Verilog and synthesized. It used a counter architecture to cut down on flop usage. 3. Layout and Packaging The entire circuit was laid out as shown in figure 3. Pads and a package were also chosen and laid out as well as shown in figure 4. The chip was LVS and DRC clean, but no post layout simulations were done. A 24 PDIP package was chosen. The package had a cavity size of 136 mils x 160 mils which fit the 1.28 mm x 1.38 mm die size. 2.4 The Coarse ADC

4 4. Conclusions Figure 3. The chip core. Figure 4. The chip core with pads. Implementing the FI-ADC was an interesting and educational exercise in chip design. Its complexity was enough to fill the 5 weeks of allocated design, simulation and layout time. Additionally, the DAC and FI-ADC were independent enough to allow each designer to independently design their half. Layout integration proved difficult. A common pitch was chosen for both the digital and analog blocks but a common width was difficult to meet. The pin placement of the sub-blocks posed an additional challenge. Since 3/4 of the chip was custom analog, most of the chip was laid out by hand. The final chip included 196 custom NMOS devices, 735 custom PMOS devices and a great number of gates, poly resistors and capacitors. There was a lot of room for improvement in this FI-ADC implementation. The comparators needed to be redesigned to be faster. They also should have used a clocked capacitor auto-zeroing technique. The poly resistor loads for each folding circuit should have been replaced with an active device circuit due to their size as shown in figure 5. In addition the poly resistor trees should have been replaced with another implementation that was not as prone to process variations. Finally, the layout of each sub-block needed to be reevaluated so that during the integration of the ADC and the DAC the two blocks fit together without long routing Figure 5. 1) resistors 2) a PMOS differential pair

5 References [1] P. Allen and D. Holberg, CMOS Analog Circuit Design. Oxford University Press, 2nd ed., 2002 [2] G. Hurst and L. Meyer, Analysis and Design of Analog Integrated Circuits. John Wiley & Sons, Inc., 4th ed., [3] S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis.Prentice Hall, [4] L. Siek et al., "Top-Down Approach in High Speed ADC," Nanyang Technological University. Please see the project's website for more details on the chip: index.html