SAR Control Logic. GADCout <9:0> Figure 1. GADC diagram architecture.

Size: px

Start display at page:

Download "SAR Control Logic. GADCout <9:0> Figure 1. GADC diagram architecture."

Alison Griffith
6 years ago
Views:

1 GADC bloc: The bloc GADC (General Analog to Digital Converter) is a general purpose 10 bit ADC used to digitize different analog voltages of the FEI4 chip. As depicted on the Figure 1 below, the GADC contains an input stage composed of an 8 to 1 analog multiplexer to select the input to convert. The architecture is a successive approximation converter (SAR), composed of a control logic, an digital to analog converter (DAC), and a comparator (see following sections for architecture details and working procedure). This input can be either the voltage from the TEMPSENS bloc to monitor the temperature of the chip, or the power supply, or the detector leakage current driven by the FEND bloc. This leakage current starts from pa and can reach up to 100 na in high radiation environment. It is converted into voltage via a resistor at the input of the GADC. The FENDbloc mirrors 5 times the detector leakage current, therefore a resistor is used to convert the current into voltage at the input of the GADC. Input voltages GADCsel<2:0> Analog Mux 8to1 Selected voltage DAC Comparator SAR Control Logic start status clk GADCout <9:0> Figure 1. GADC diagram architecture. GADC specifications: SPECIFICATION VALUE UNITS Resolution 10 bit Conversion time 1 us Input voltage range to convert 0 to 900 (VrefGDAC) mv Area 180 x 150 = µm² Differential non linearity < ½ LSB (<500 µv) Table 1. Specifications.

2 GADC Interface: Special Notes: 1) Digital and Analog signals are in different colors 2) Positive logic is assumed Pin Name IleakIn Vtemp VrefGADC VBias_comp GADCsel GADCstart GADCstatus GADCclk Input From Output TO FEND TEMPSENS Voltage reference TEMPSENS Control Control CKGEN Control INOUT? Description Mirrors 5X the detector DC leakage current. Voltage for temperature measurement Input voltage reference for the DAC Gate voltage Vg of the TEMPSENS lpnmos 1uA bias current mirror in order to bias the comparator Input selection via the analog Mux Ask for a conversion when high high when the conversion is done, low when ongoing. 10 MHz clock for control logic GADCout Control 10 bit GADC value Specifications if any 900 mv Comments and requests I/V conversion of this detector leakage current via the input resistor 3 bit selection for the 8 to 1 analog multiplexor The conversion start only if when GADCstart goes high while GADCstatus being low 10 MHz extracted from the 40 MHz general clock GADCdisable Control Active high. GADC bloc is ON when low and OFF when high. Table 2. GADC bloc interface (I/O).

3 GADC symbol : Figure 2. GADC symbol. GADC architecture : TOP VIEW Figure 3. GADC top view.

4 DAC 10b Figure 4. DAC 10b schematic.

5 Rmsb = 563 ohm Rlsb = 9.5 kohm Figure 5. DAC Matrix bloc schema. 10bit input Analog Mux output voltage Figure 6. DAC Matrix bloc principle diagram.

6 Figure 7. DAC Matrix bloc layout.

7 Figure 8. Decoder 2 to 4 schematic.

8 Figure 9. Decoder 2 to 4 layout. Figure 10. Decoder 4 to 16 schematic.

Figure 11. Decoder 4 to 16 layout. The resistors values (563 ohms for MSBs and 9.5 kohms for LSBs) of the DAC have been tuned to get a linearity under the ½ lsb (<500 µv).

9 Figure 11. Decoder 4 to 16 layout. The resistors values (563 ohms for MSBs and 9.5 kohms for LSBs) of the DAC have been tuned to get a linearity under the ½ lsb (<500 µv). CONTROL LOGIC (SAR) The control logic is a successive approximation algorithm. It consists in a dichotomy procedure that allows to convert the analog input voltage to 10 bit in 10 clock periods. The associated code is the following : ///Verilog HDL for "work", "SAR" "behavioral" module SAR ( count, status, discri_state, start, clk ); parameter nbits = 10; output [0:(nbits-1)] count; output status; // show if a conversion is running input discri_state; // output of the comparator (discri) input start; // positive edge conversion activation (if no conversion is running) input clk; // 10 MHz clock reg [0:(nbits-1)] count; reg status; integer i; initial begin count[0:(nbits-1)] = 'h002; status = 0; end // bit Conversion start) clk) count[0:(nbits-1)] = 'h001; status = 1; for(i = nbits-1 ; i >= 0 ; i = i-1 ) clk) //SAR occupé

simulation result that validate the verilog code: Figure 12.

10 if(discri_state == 0) begin count[i] = 1; count[i-1] = 1; end else begin count[i]=0; count[i-1] = 1; end end status = 0; end endmodule An example of simulation result that validate the verilog code: Figure 12. Successive approximation control logic simulation. The synthesis of the code is on going to get final layout.

11 ANALOG 8 TO 1 MULTIPLEXER (MUX8to1) Figure 13. Analog 8 to 1 multiplexer schematic.

12 Figure 14. Analog 8 to 1 multiplexer layout.

13 Figure 15. Analog switch TGATE schematic. Figure 16. Analog switch TGATE layout. The linearity of the TGATE switch on the 0 to VDD range has been verified by simulation.

14 COMPARATOR Figure 17. Comparator schematic. The comparator is currently biased with a 15 µa current. As the input voltages are DC signals, we compensate the offset of the comparator doing 2 times the 10 bit conversion, first with input voltage on input 1 of the comparator and VDACout on the input 2 and second with the contrary (input voltage on comparator input 2 and VDACout on input 1). Then we take the average of the two values to get the offset free number. GADC hardening : 10 bit DAC is based on resistors voltage divider in order to minimize process&mismatch dispersion and radiation impact. Indeed relative expressions are used to cancel component parameters drifts. Moreover a 2 step digitization scheme is setup for the same reasons. TO DO : 1. Verilog synthesis of the 10 bit SAR logic (code ready), 2. Tuning of the comparator component to keep sensitivity within ½ lsb on the input voltage dynamic range (ideally 0 to 900 mv but difficult for input voltage under 300 mv) 3. post-layout verifications

Assoc. Prof. Dr. Burak Kelleci

DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING ANALOG-TO-DIGITAL AND DIGITAL- TO-ANALOG CONVERTERS Assoc. Prof. Dr. Burak Kelleci Fall 2018 OUTLINE Nyquist-Rate DAC Thermometer-Code Converter Hybrid