Simultaneous Co-Test of High Performance DAC-ADC Pairs May 13-28

Transcription

1 Simultaneous Co-Test of High Performance DAC-ADC Pairs Adviser & Client Members Luke Goetzke Ben Magstadt Tao Chen Aug, 2012 May,

2 Agenda Project Description Project Design Test and Debug Results 2

3 Project Description Overview Algorithm 3

4 Simultaneous Co-Test of High Performance DAC-ADC pairs Goal to create a PCB all in one solution with A user interface DAC signal generator ADC digitizer for Data converter test Data collection Co-test algorithm verification use by ISU grad students (supported by T.I.) 4

5 Simultaneous Co-Test of High Performance DAC-ADC pairs Ability to simultaneously test DAC-ADC pairs Distinguish individual non-linearities using a data analysis algorithm Very new concept research project Need: Reduced test cost and time Reduce need of high performance test equipment 5

6 Simultaneous Co-Test of High Performance DAC-ADC pairs Traditional Test Costly Time inefficient ADC Higher precision wave generator SINE Pure wave generator ADC ADS 8321 Higher bit precision DAC DAC High performance DMM Higher bit precision ADC DAC DAC 7631 ADC High Precision 6

7 Simultaneous Co-Test of High Performance DAC-ADC pairs New test method (this project) No needed costly precision equipment DAC ADC pair (equal resolution) 2 filters with coherent test detailed data analysis Our design also handles traditional test DAC DAC 7631 ADC ADS

8 Requirements Functional 100k SPS DAC/ADC 16 bit precision parts Low noise & offset in filter design Comparable data to standard test methods Coherency Non functional Low cost design Modular Reconfigurable Easily redesigned Small, debugable and reusable 8

9 On Going Research: Non-Linearity Algorithm DAC -> Nonlinear Oscillator Produced sine wave Pass through two filters individually Filter 1: RC filter Filter 2: RR attenuator ADC -> digitizes signal 9

10 On Going Research: Non-Linearity Algorithm Result: Two different output waves Same amplitude at fundamental frequency Difference in amplitude or phase attributed to difference in filters Filters will only affect the DAC s non-linearities Algorithm uses this data to distinguish non-linearities of the ADC & DAC 10

11 Power (db) Power (db) Coherency f in f s = N cycles M samples Non-coherency causes spectral leakage 0 Power Spectrum: Non-Coherent 0 Power Spectrum: Coherent Frequency (Hz) Frequency (Hz) 11

12 Project Design Fall 2012 initial design Spring 2013 new (final) design 12

13 Current Project Design Goal of project is to Develop a way to provide the data Not to analyze the data PCB to house DAC/ADC and filters Plug in FPGA controller (verilog) Matlab user interface 13

14 Project Development F12 Design (currently scrapped) No microcontroller/all in one PCB design Use LabView to control and communicate with the board Large multilayer board (memory modules, digital interfaces) Communication with RS232 (very slow) Too costly Error prone, long build and debug time S13 Design (spin of F12) FPGA controller No added cost Plug in - digital control Data storage Interface to computer At least 10x cheaper Easily redone, simple construction, modular (future work) 14

15 Fall 2012 Design (currently scrapped) Limiting requirement = no uc or FPGA Analog Digital Control Analysis 15

16 Fall 2012 Design (currently scrapped) Wave Setup Data In/out Binary 16bit Board indicators + Control Data In/out Voltage +/-2.5v 16

17 Fall 2012 Design (currently scrapped) Completed Designed Schematics Serial (rs232) Interface to LabView DAC + DAC memory ADC + ADC memory Filters Derived controls Simulation Layout 17

18 Fall 2012 Design (currently scrapped) Simulation / Software TINA TI Filter Design LabVIEW Controller Simulation Timing Diagram Verilog Altium (DAC / Memory; ADC / Memory; Control signals; Serial interface) Digital Simulation PCB design PCB layout 18

19 Transition Design 1 Difficult and very large layout Price Quote: TOO high Construction and debug Expected to be lengthy Able to complete project? Redesign Modern approach use FPGA/microcontroller Focus on cost reduction 2 weeks 19

20 Current Project Design PCB layout Major component of project Layout Parts Solder 20

21 Current Project Design PCB Comparison Fall 2012 initial PCB design (no FPGA) ~4x bigger (not as functional) Spring 2013 final PCB design (plug in FPGA) 21

22 Spring 2013 Design (final) FPGA controller (Verilog) - No added cost Digital controls Data storage Interface to computer PCB to house DAC/ADC and filters Matlab user interface Matlab analysis (prior and future work) At least 10x cheaper Easily redone, simple construction, modular, small 22

23 Current Project Design Top level 23

24 Current Project Design PCB Reused filter schematic from initial design (T.I. parts) Added digital lines to a 40pin GPIO connector to FPGA Capable of new and traditional test Multi-setup capability 2 layers, < 60in^2 (student discount = cheap) 24

25 Current Project Design - Filter Issue: Analog filter design: high performance requirement: single ended input/ different output Very low offset Very low noise Very low distortion Solution: Non-inverting 4 stage buffer/filter configuration High Performance Op-Amp s Simulated with TINA-TI 25

26 Current Project Design Filter TINA - TI 26

27 Current Project Design Filter Design output Expected results 27

28 Current Project Design Design Risk Mitigation Thorough analog simulation (in: TINA TI) Thorough digital simulation (Verilog) Multiple Test Points Multiple Debug Paths Varied Input Ports Clock Reference Voltages 28

29 Current Project Design - FPGA Altera Cyclone II FPGA DE2 board with memory chips From CprE class (readily available) FPGA (Verilog) Controls a mixed-signal board through GPIO pins Stores collected data Handles all communication with computer (provided software) Easy use/modular/reprogrammable/easy debug and construction/ cost effective 29

30 Current Project Design - Verilog FPGA Verilog control code Setup on board memory (Challenge in itself) 24 clock cycle 100ksps parts => ~2.4MHz operating clock Program DAC (refer to datasheet) Received ADC (refer to datasheet) FPGA Computer interface Provided by Altera Easy data program/extract from memory chip (direct) 30

31 Current Project Design - MATLAB Matlab GUI and user interface Creation of wave signal data files to send to DAC Many characteristics and types available (Coherency Calculator) Analyze received data file sent from ADC (future user) Flexible code (future user) 31

32 Results Initial Final (proposed) Final (traditional) 32

33 Results Output data transported back to Matlab Observe output spectrum Main interests Coherency Fundamental frequency Harmonics Other high level spurs Noise floor 33

34 Power (db) Results Initial (bad) Power Spectrum Frequency (Hz) 34

35 Results Debugging bad results High level spurs caused by clock jitter No available clock generator with low enough jitter Solution: FPGA clock has low enough jitter level Jitter affects on SNR in a 16b ADC (Linear Technology paper) 35

36 Results ADC-DAC Co-test 36

37 Results Testing ADC with high precision wave generator 37

38 Results Testing DAC with high precision 24-bit ADC 38

39 Results Summary of Proposed Coherency was obtained in the proposed test Noise floor was dropped below the -100dB level Signal s largest spurs were harmonics Comparable to datasheet's spectrums 39

40 Results Traditional Test Summary Coherency was not obtained Has been shown that this can be corrected through analysis algorithm to obtain accurate results Signal s largest spurs were harmonics Noise floor is yet to be seen and will be determined once the non-coherency algorithm is applied 40

41 Conclusion 41

42 Project Summary Product Tools Used PCB design TINA - TI PCB layout Altium FPGA/ Verilog prog. Quartus II / Bench equipment Matlab GUI Matlab Soldered PCB Solder iron PCB debug Bench equipment Cost [$] PCB manufacture Parts FPGA Precision tools Tools Used $33.00 Advanced Circuits, Aurora CO $80.00 TX Instruments / Analog Devices $0.00 Altera Cyclone II DE2 $0.00 Audio Precision/ 24b ADC evm. total project cost $

43 Conclusion Project goal was met Board successfully generated, transmitted, and received waves New test style Traditional style Coherency -> shorter test time Future work Expand to multiple ADC / DAC interfaces Use board in research test to verify algorithms and characterize board further 43

44 Questions 44

45 Extra Slides The following slides are not apart of the presentation, but are the schematics used in our designs. - Design 1 schematics - Serial interface test (of design 1) - Design 2 schematics with notes 45

46 Fall 2012 Design (currently scrapped) Schematic: Top Level 46

47 Schematic: Serial Interface Fall 2012 Design (currently scrapped) 47

48 Schematic: DAC / Memory Fall 2012 Design (currently scrapped) 48

49 Schematic: Filter Fall 2012 Design (currently scrapped) 49

50 Schematic: ADC / Memory Fall 2012 Design (currently scrapped) 50

51 Schematic: Power Supplies Fall 2012 Design (currently scrapped) 51

52 Schematic: Clocks Fall 2012 Design (currently scrapped) 52

53 Schematic: Controls 1 Fall 2012 Design (currently scrapped) 53

54 Schematic: Controls 2 Fall 2012 Design (currently scrapped) 54

55 Schematic: Controls 3 Fall 2012 Design (currently scrapped) 55

56 Simulation: LabVIEW Fall 2012 Design (currently scrapped) I/o scheme: ha5 -> 8 b Lblue CTS 25% duty 9.6kHz (byte transfer rate) start on rising edge of clock Pink Data line + 1 space parity Very repeatable 56

57 Final Design Schematic: Block Diagram 57

58 Final Design Schematic: Power Supplies Signal Name Connector Name Description VDDB J4 Digital part power supply, 5V DGNDB J5 Digital part ground, it is connected to the FPGA ground VCC J2 Analog part, +15V, power supply for some op amp VSS J1 Analog part, -15V, power supply for some Op Amps +5VA J6 Analog part, +5V, power supply for DAC, ADC, some Op Amps -5VA J7 Analog part, -5V, power supply for DAC, some Op Amps AGND J3 Analog part ground 58

59 Final Design Schematic: Reference 59

60 Final Design Schematic: Digital 60

61 Final Design Schematic: Filter Pat h Input Filt. Output purpose co. 1 16b DAC 1 16b ADC simult. yes 2 16b DAC 2 16b ADC simult. yes 3 16b DAC n/a 16b ADC debug yes 4 AP 1 16b ADC ADC test no 5 AP 2 16b ADC ADC test no 6 AP n/a 16b ADC ADC test no 7 16b DAC 1 24b ADC DAC test no 8 16b DAC 2 24b ADC DAC test no 9 16b DAC n/a 24b ADC DAC test no 10 AP 1 24b ADC filter char n/a 11 AP 2 24b ADC filter char n/a 12 AP n/a 24b ADC filter char n/a *AP = Audio Precision, precision sine wave generator 61