The Design and Construction of a DDS based Waveform Generator

Transcription

1 1 The Design and Construction of a DDS based Waveform Generator Darrell Harmon Abstract A direct digital synthesis (DDS) based signal generator was designed and constructed to cover the frequency range of DC to 20 MHz. The generator is capable of producing Sine and Square waves up to 20 MHz, and can produce arbitrary waveforms whose frequency is limited by a 23 MHz low pass filter. The arbitrary waveform generator is capable of generating Triangle waves at frequencies up to 7 MHz. This signal generator has very high frequency accuracy due to the use of direct digital synthesis. The signal generator is easy to modify due to the FPGA based architecture. Also, many different types of modulation are possible. Index Terms DDS, CORDIC, FPGA, DSP, Signal Generator I. INTRODUCTION A signal generator is useful for testing many types of circuits. Most low cost signal generators drift significantly in frequency, and cannot be controlled by a computer. Recently, high speed DACs and FPGAs capable of generating high frequency signals in real time have become available [1]. This report discuses the design and construction of an FPGA based signal generator. II. SPECIFICATIONS The signal generator will be able to generate sine, square and triangle waves from 1 Hz to 20 MHz. The output will have a 50 ohm impedance. The peak output voltage into a 50 ohm load will be variable from 50 mv to 5 V. The signal generator is to have the ability to be controlled by a computer. DAC aliases should be at least 60 db below the carrier. Harmonics should be kept 40dB below the carrier for frequencies greater that 1 MHz and 60 db below the carrier for frequencies less than 1 MHz. III. SYSTEM OVERVIEW The signal generator consists of 5 major parts: the computer used for control, the microcontroller, the FPGA, the DAC and the analog signal processing section. A computer running control software sends commands via a RS232 serial port to the microcontroller in the signal generator. The microcontroller passes these commands to the FPGA. The microcontroller is also responsible for initializing the FPGA and loading the configuration bitstream. The FPGA is responsible for the digital signal

2 2 processing. The FPGA outputs data to a high speed parallel DAC, and the output of this DAC is sent to the analog signal processing board. The analog signal processing board provides filtering, switchable attenuation, amplification and sine to square wave conversion. 80 MHz sampling rate chosen and the 32 phase accumulator chosen, f = ftw Two methods of converting the phase value to a sample value are used. The first is by using the CORDIC (COordinate Rotation Digital Computer) algorithm. CORDIC allows high speed vector rotation in FPGAs and ASICs. CORDIC is very efficient IV. DIRECT DIGITAL SYNTHESIS The signal generator uses Direct Digital Synthesis (DDS) techniques to generate the desired waveforms. As a compromise between an attainable sampling rate and the complexity of the required reconstruction filter, a sampling rate of 80 MHz was chosen. The phase accumulator is the basis of the DDS system. Every clock cycle, the phase accumulator is incremented resulting in linearly increasing phase and this phase value is converted to an amplitude value which is output to the DAC. The rate of the increase of phase determines the frequency. In the FPGA, the phase is represented by a 32 bit unsigned integer. In the FPGA implementation, a phase value of 360 degrees is represented by This causes the phase accumulator overflow to occur at the same time as the phase reaches 360 degrees. The phase accumulator overflow can be ignored due the overflows occurring simultaneously. The frequency can be determined by formula f = fs ftw 2 n where ftw is the value added to the phase accumulator every cycle, f s is the sampling rate and where n is the number of bits in the phase accumulator. For the both in terms of gates and power. Vector rotation can be used both to generate sinusoids and perform modulation [2]. A 14 bit CORDIC will be used. This will provide for 14 bit amplitude and phase resolution. With CORDIC, setting the input to a constant while linearly increasing phase produces a sine wave. Applying a signal to the input modulates the signal. Alternately, a look up table can be used to convert phase values to amplitude values. The most significant 10 bits of the phase accumulator are used to address a ROM to provide output samples. In place of a ROM, a dual port SRAM can be used allowing the waveform to be modified at any time. The second port is connected to a microcontroller which is capable of generating and loading waveforms. A 16384x14 SRAM was used. This SRAM was made up of x1 Xilinx blockram blocks. The Xilinx Spartan 3 XC3S400 FPGA contains 16 blockram blocks. The use of a look up table has the advantage of being capable of generating arbitrary waveforms. When sine wave or square wave is selected,

3 3 the CORDIC is used. For the generation of other waveforms such as triangle, the lookup table is loaded with samples of the wave to be generated. modulating signal to the phase. A full scale modulating signal will shift the phase from +180 degrees to -180 degrees. V. MODULATION Several modulation types can be achieved by implementing a modulator in the FPGA. AM, FM and PM were included. The modulation source is a second CORDIC and phase accumulator. This provides a complex sinusoid which can be varied in amplitude. Single sideband modulation can be achieved by simply connecting complex modulating signal to the modulator CORDIC. Double sideband can be achieved by connecting the real part of the modulating signal to the real input of the modulator CORDIC and setting the imaginary input of the modulator CORDIC to 0. An adjustable offset to the real input of the modulator CORDIC is provided and allows for adding a carrier. This allows both DSB-SC and DSB-LC modulation. The percentage of modulation is fully adjustable from 0% to 200% (overmodulation) for the DSB-LC case. If amplitude modulation is not desired, the input to the modulating CORDIC is set to a constant resulting in sinusoidal output. Frequency modulation is achieved by adding the modulating signal to the frequency tuning word. The modulating signal is divided by 256 so that the maximum frequency deviation is khz. The frequency deviation can be scaled by adjusting the modulating CORDIC amplitude. Phase modulation is implemented by adding the VI. DAC, FILTER The Burr Brown DAC904E was used in the signal generator. This part is a 14 bit current steering parallel DAC capable of operating at up to a 160 MHz sampling rate. The clock frequency of 80 MHz was chosen to allow for a realizable reconstruction filter to be used. The DAC has a 20 ma differential current output, and only one half of the differential output was used. This output was terminated to ground with 50 ohms and connected to a BNC connector on the DAC board. The other output was grounded. This configuration results in a signal which swings from 0V to 0.5 V when connected to a 50 ohm load. An reconstruction filter is required to remove the aliases generated by the DAC. It was desired that all aliases be at least 60 db below the fundamental output power. It was determined that the worst case alias would result at an output frequency of 20 MHz, producing a 60 MHz alias at dbc. This meant a filter would be required which would pass 20 MHz relatively unattenuated, but attenuate by at least 50 db at 60 MHz. A 5th order active Chebyshev filter was considered, but the phase distortion of the arbitrary waveforms could not be tolerated. The reconstruction filter was implemented as a 7th order Butterworth filter. Due to the high cost and

4 4 complexity of an active filter at these frequencies and the small size of the inductors required, a passive LC filter was used. Surface mount inductors and capacitors were used. The values of the L1 150nH L2 560nH L3 560nH L4 150nH components were calculated from a table found in appendix H of [3]. The 560 nh inductors were 0805 C1 180pF C2 270pF C3 180pF size wirewounds, and the 150 nh inductors were 0603 size wirewounds. The capacitors were all NP0 dielectric 0603 size multilayer ceramic capacitors. Exact capacitor and inductor values were unavailable. The closest available capacitors and inductors to the required values were used resulting in a cutoff frequency of 23 MHz. The attenuation of 50 db at 60 MHz is maintained using these values. See Table I or Figure 1 for the filter schematic and values. The filter has a 50 ohm input and output impedance. The input impedance is matched to the output impedance of the DAC board and the impedance of the interconnecting cable. Figures 2 and 3 were obtained using a HP4195A network analyzer, and show that the filter meets the specification. The attenuation at 60 MHz is 57.3 db. The attenuation is greater than 60 db for all frequencies above 63 MHz up to the 500 MHz maximum frequency of the network analyzer. The filter has an 0.6 db loss at DC due to the inductor resistance and a 1.2 db loss at 20 MHz due to the skin effect in the wirewound inductors. The DC loss will be compensated for by amplifier gain. The AC loss could be corrected in software by increasing the gain as frequency increases. Fig MHz 7th Order Butterworth LC Lowpass Filter TABLE I 20 MHZ 7TH ORDER LC LOWPASS FILTER COMPONENT VALUES Component Calculated Value Value Used L1, L4 177 nh 150 nh L2, L3 717 nh 560 nh C1, C3 198 pf 180 pf C2 242 pf 270 pf The output of the filter was connected to an OPA695 current feedback amplifier in an inverting configuration with a gain of 8.43 with an input impedance of 50 ohms. A DC offset was also provided at this point so that the 0 to 0.5 V signal from the DAC swings from -2V to +2V at the output of the amplifier. The OPA695 provides a bandwidth of 450 MHz at a gain of 8 which is far greater than the required bandwidth of 20 MHz. VII. SINE TO SQUARE WAVE CONVERSION It was decided that the best way to produce sine waves would be to pass the sine wave through a comparator. Several alternatives were considered including switching between two voltage sources,

5 5 DC offset of the resultant square wave. VIII. MULTIPLEXER Both sine/arbitrary and square waves are produced by the preceding circuitry. A multiplexor is needed to select which signal should be sent to the output amplifier. Also, attenuation is needed to provide for lower output levels. The Analog Devices AD input video multiplexor was selected for Fig. 2. Reconstruction filter response - sweep from 0 to 500 MHz. 10 db/div. The marker is placed at 60 MHz where the attenuation is 57.3 db. this purpose. This part has a bandwidth of 700 MHz and has a built in buffer amplifier. The input impedance is very high. A pair of 20 db attenuators were constructed from 180 Ωand 20 Ωresistors. Both attenuated and unattenuated square wave and sine wave/arbitrary waveform inputs were connected to the multiplexor. Any of the four inputs can be selected via software. IX. POWER AMPLIFIER The power amplifier must be able to swing from Fig. 3. Reconstruction filter response - sweep from 0 to 30 MHz. 1 db/div. The diagonal line is the phase shift. +10 V to -10 V into a 100 ohm load. This is necessitated by the need to swing from +5 V to -5 V into a 50 ohm load while providing a 50 ohm directly using a comparator and limiting amplifiers. The Texas Instruments OPA699 limiting amp was chosen. It provides extremely high speed with a gain bandwidth product of 1 GHz. This amplifier provides upper and lower limit inputs, and clips the output signal to these limits. The limit inputs were driven using a pair of slow serial DACs. The DACs allow for adjustment of both amplitude and output impedance. A 50 ohm series resistor is used on the output of the amplifier to set the output impedance. This resistor is outside the feedback loop. The amplifier needs a slew rate of at least 4000 V/µs to be able to achieve a 5 ns rise and fall time. Originally, the Texas Instruments THS3061 current feedback amplifier was selected as the power

6 6 amplifier. This amplifier is capable of being powered by a±15 V supply and providing an output current of 145 ma. The high power dissipation is handled by a heat sink tab on the bottom of the package. The device has a bandwidth of 260 MHz at the required non inverting gain of 5. The slew rate of the THS3061 is 7000 V/µs. The opamp is unprotected, so external protection will be required in order to not exceed any absolute maximum ratings in the U4 THS3061 event of an output short. This opamp appeared to be exactly what was needed on paper and in SPICE, but latched up in operation. It appeared that the latchups were caused by too high slew rate. The peak voltage across the opamp inputs would increase to 150 millivolts when the slew rate of the output reached approximately 7000 V/µs. Any increase in the input slew rate from this point would cause a latchup and the amplifier would draw approximately 150 ma from the power supply. The addition of an RC lowpass filter prior to the power amp resulted in either too much rounding of the square wave edges or was ineffective at solving the problem depending on the value of the capacitor. Current limiters were added to the THS3061 supplies to prevent it from being destroyed upon latchup. The were implemented as shown in Figure 4. There were no other amplifiers that could be found to meet the supply voltage, output current and slew rate specifications simultaneously. The Texas Instruments OPA695 current feedback Fig. 4. The current limiting circuit for the negative supply used with the THS3061 amplifier was used as the power amplifier. This amplifier uses a±5 V power supply, and the output can swing from +4 V to -4 V. The slew rate is 4300 V/µs. The amplifier has a bandwidth of 1.4 GHz at a non inverting gain of 2. The amplifier was used in a non inverting configuration with a gain of While the signal generator was unable to meet the output voltage specification using the OPA695, all other specifications were preserved with this substitution. The OPA695 is able to safely drive a 50 ohm load, so in the event of an output short, it will be protected by the 50 ohm series termination. -15V X. RESULTS The measured output frequency error was extremely small. An Instek GFC-8131H frequency counter was used for these measurements. The counter has an uncertainty of 5 ppm which is greater than the measured errors. It is possible

7 7 the the errors are higher than as measured. More accurate equipment was unavailable. The results are presented in Table II. The large error at 1 Hz is due to rounding of the frequency tuning word. The resolution is approximately Hz. All other frequencies measured resulted in an error of less than 4 parts per million. The clock oscillator used is in figure 6. Using a 1.8V peak setting results in an acceptable distortion level. The minimum output amplitude of 50mV into 50 ohms was verified as seen in Figure 7. The signal generator is capable of producing smaller signals, but the noise level will increase as amplitude decreases as less bits are used of the DAC. only specified to be within 30ppm of 80 MHz. The maximum frequency error is the oscillator frequency error plus the rounding error of up to Hz. TABLE II FREQUENCY ACCURACY Setting Measured Error (Hz) Error (ppm) 1 Hz Hz khz khz khz khz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Fig MHz Sine wave The output of the signal generator was measured in the time domain using a Tektronix 7903 oscilloscope with 7A19 and 7B92A plugins. This oscilloscope has a bandwidth of 500 MHz and a risetime of 800 picoseconds. The output was measured in the frequency domain using an HP 4195A spectrum and network analyzer. This instrument provides resolution bandwidths down to 3Hz and Fig MHz Sine wave : Amplitude = 2 V peak very good frequency accuracy. The signal generator was determined to clip at 1.9 volts into a 50 ohm load. This is illustrated The spectrum of the sinusoidal output is shown in figures 8, 9 and 10. Figure 8 shows the generation of a MHz sine wave at 1 Volt peak (10

8 8 Fig MHz Sine wave : 50 mv peak Fig MHz MHz Sine wave : 1 V peak, sweep from DC to dbm). There is a second harmonic approximately 60 db below the carrier. This is due to distortion in the amplifiers. There is also a signal at MHz which is also approximately 60dB below the carrier. The origin of this signal is unknown. It may be due to rounding error. Figure 9 displays the spectrum of a 19 MHz sine wave. The 135 khz modulation that is seen was determined to be due to the 1.2V FPGA core voltage switching power supply which operates at 135 khz. The modulation Fig MHz 1 V peak Sine wave spectrum - 1 MHz span is 53 db below the carrier. This problem could be solved at the cost of power consumption by using a linear regulator. Figure 10 shows that the carrier itself is very clean. The noise floor is much lower due to the small resolution bandwidth of 10 Hz used. Using this resolution bandwidth with a larger span would take too long to be practical. The square wave function worked as expected. The rise and fall times of a 20 MHz 1 volt peak square wave were measured at 3 nanoseconds. This can be seen in Figures 11 and 12. The risetime is slightly longer at lower frequencies increasing to 100 ns at 1 khz. This could be improved by using the arbitrary mode and generating an approximate square wave as input to the comparator. Figure 13 is the spectrum of a 20 MHz square wave generated by the signal generator. The 13th harmonic is clearly visible. There is a significant amount of power in even harmonics. This is due to the square wave being non-symmetric which is

9 9 Fig MHz 1 V peak Sine wave spectrum - 1 khz span Fig MHz Square wave risetime detail Fig MHz Square wave - 1 volt peak Fig MHz Square wave spectrum caused by an offset error at the comparator input. The 2nd harmonic is approximately 35 db below the fundamental. Triangle waves were generated by using the arbitrary waveform generator mode. The lookup table was loaded with a triangle wave calculated by Fourier series. The number of harmonics was selected so that none would alias. Figure 14 was generated using 39 harmonics in the look up table. The harmonics above 23 MHz were attenuated by the filter. Figure 15 illustrates a 5 MHz triangle wave. The 5th and higher harmonics were greatly attenuated by the reconstruction lowpass filter. The lookup table was loaded with harmonics through the 7th. A sawtooth wave was also used to demonstrate the arbitrary waveform generator. Figure 16 demonstrates the generation of a 1 MHz sawtooth wave. Figure 17 demonstrates a 1 MHz square wave band limited to 19 MHz. The lookup table values were calculated by Fourier series. Figure 18 show the signal generator outputting

10 10 Fig MHz Triangle wave Fig MHz Sawtooth wave Fig MHz Triangle wave Fig MHz square wave limited to 19th harmonic double sideband large carrier with 100% modulation. The carrier frequency is 1 MHz and the modulating frequency is 10 khz. Figure 19 is the same except for the modulation was changed to 50%. Figure 20 illustrates double sideband suppressed carrier. Figure 21 is the spectrum of the signal generator output when performing double sideband large carrier modulation (AM). The spectrum is as expected with the addition of second harmonic distortion of the modulating signal 55 db below the power of the sidebands. Figure 22 is the spectrum of the signal generator output when performing double sideband suppressed carrier modulation. This modulation is the same as AM with the carrier removed. The same distortion exists. Figure 23 is the spectrum of a wideband FM signal generated with the signal generator. The frequency deviation is set to 75 khz which is the same as used in broadcast FM radio. No measurable distortion was noted. The AM and FM modulation was also tested successfully using a radio receiver.

11 11 Fig MHz DSB-LC with 10 khz 100% modulation Fig MHz DSB-SC with 10 khz modulation Fig MHz DSB-LC with 10 khz 50% modulation Fig MHz DSB-LC with 5 khz modulation XI. CONCLUSION The use of Direct Digital Synthesis provides many advantages over a traditional signal generator. These include excellent accuracy of output frequency and extreme flexibility for modulation. The use of the FPGA allows the user to make any changes desired. There are still many things that could be improved about the signal generator. The user interface could be made simpler than the current command line program. A physical control panel could be constructed if desired. The computer interface could be changed from RS232 serial to USB. XII. APPENDICES 1. Schematics (Analog board, DAC board, DSPcard) 2. FPGA logic Verilog listing 3. AD8184 Multiplexor datasheet 4. OPA695 Opamp datasheet 5. DAC904E DAC datasheet 6. OPA699 Opamp datasheet

12 12 Fig MHz DSB-SC with 5 khz modulation Fig MHz wideband FM with 15 khz modulation and 75 khz deviation REFERENCES [1] G.-J. van Rooyen and J. G. Lourens, A quadrature baseband approach to direct digital fm synthesis, IEEE Transactions on Broadcasting, vol. 46, no. 3, Sep [2] Ray Andraka, A survey of cordic algorithms for fpga based computers, ACM/SIGDA sixth international symposium on Field programmable gate arrays, Monterey, CA, Feb [3] Paul Horrowith and Winfield Hill, The Art of Electronics, Cambridge University Press, second edition, 1989.