FMC ADC 125M 14b 1ch DAC 600M 14b 1ch Technical Specification

Transcription

1 FMC ADC 125M 14b 1ch DAC 600M 14b 1ch Technical Specification Tony Rohlev October 5, 2011 Abstract The FMC ADC 125M 14b 1ch DAC 600M 14b 1ch is a FMC form factor card with a single ADC input and a single DAC output. Two independent VCXO s are used to set the ADC and DAC sapling rates. A clock input is provided from which the VCXO s can be locked. The FMC connector is Low Pin Count.

2 History of Changes Version Date Author(s) Changes /4/11 T. Rohlev Initial release 2.0 2/23/12 T. Rohlev Everything 2.1 3/6/12 T. Rohlev Trigger termination, FMC connector map This document may have been updated since you printed it. In case of doubts, please look in for the latest version and compare its History of Changes with yours.

3 Fig. 1 Block diagram of FMC ADC 125M 14b 1ch DAC 600M 14b 1ch.

4 1 Features Single high accuracy 14-bit ADC input channel with a sampling rate of up to 125 MSPS. ADC input signal is AC coupled with an input level from 1.25 Vpp to 2.25 Vpp into 50Ω depending on the choice of matching network components. The ADC sample clock is produced from an on-board digitally controlled VCXO. Single 14-bit DAC output channel with a sampling rate of up to 600 MSPS. DAC output is AC coupled with a maximum level of up to 2 Vpp into 50Ω. The DAC sample clock is produced from a second on-board digitally controlled VCXO. A DC coupled bi-directional trigger (or clock I/O) is available that connects directly to the carrier board. Signaling rates are in excess of 250 Mbps out, 400 Mbps in. A low jitter high speed 4x4 crosspoint switch in combination with two buffered outputs can provide any combination of VCXO outputs or carrier board signals from DC to 300 MHz. 2 General Description The FMC ADC 125M 14b 1ch DAC 600M 14b 1ch is a mezzanine card in a FMC (low pin count) form factor. It is a general purpose high performance single channel data acquisition and signal generation card. The ADC input is 14 bit with a maximum sample rate of 125 MSPS. The ADC input is AC coupled with a peak input signal from 1.25 to 2.25 Vpp into 50Ω depending on the users choice of matching network components. The ADC input circuit can be optimized for signals from 15 MHz to 200 MHz by the choice of filter (and matching network components). In the current configuration the circuit has been optimized for a operation around 40 MHz signal with a 2.25 Vpp signal. A high order anti-aliasing filter with a 3 db cut-off of 56 MHz precedes the ADC. The ADC clock is generated by an on-board low jitter VCXO which is digitally controlled from the carrier card. Accuracy in excess of 12.5 effective bits can be achieved for inputs up to 70 MHz. The DAC output is 14 bit with a maximum sample rate of 600 MSPS. The DAC output is AC coupled with a peak signal of 2 Vpp into 50Ω. An onboard low pass reconstruction filter is provided. The cut off frequency can be changed from 40 MHz to over 600 MHz by replacing the filter. The DAC clock is generated by another on-board low jitter VCXO which is digitally controlled from the carrier card. The card has a high performance low jitter 4X4 LVDS crosspoint switch. The switch inputs are both of the VCXO s in addition to two LVDS signal pairs from the carrier board. The switch outputs are 2 LVDS pairs sent back to the board on the dedicated CLK0,1_M2C connector pins, and 2 LVTTL co-ax outputs on the front of the card. The LVTTL outputs are capable of driving a 50Ω load with a signal in excess of 2Vpk at a frequency/data rate in excess of 275 MHz (1Vpk in excess of 350 MHz). The switch is fully programmable so than any of the inputs can be sent to any, or all, of the outputs. A user provided clock/trigger can be sent from a connector on the front of the card to the carrier. This clock is DC coupled, TTL tolerant, with a maximum trigger/clock rate of 400 Mbps in. The same connector can also output a LVTTL level clock/trigger from the carrier card in excess of 250 Mbps. Each card is equipped with a digital (1-Wire) thermometer which also carries a unique 64-bit serial code to identify the board.

5 3 Input Channel The input channel is based around the AD9255 ADC from Analog Devices. This is a 14-bit 125 MSPS convertor with excellent dynamic properties (capable of 12.7 ENOB with a 70 MHz input). However, this ADC has an unbuffered, switched capacitor, input so care must be taken in designing the matching circuit. Since we are aiming for the ultimate in low noise performance a passive input circuit was chosen to avoid the degradation of the ADC s SNR by the noise figure of an amplifier. A standard input architecture of anti-aliasing low pass filter, center-tapped transformer, symmetric LRC matching network was chosen. The input impedance vs. frequency data, in both track and hold mode, for the ADC is provided by Analog Devices. The input matching network can been optimized for the following parameters depending on the preference of the user: Gain. Operating frequency. Input return loss. Minimize effect of voltage glitch between track and hold mode. Compensate for the gain slope of the filter and transformer at the operating frequency. The following circuits show a selection of possible optimizations: 40 MHz: 4.28 db Peak input signal: 0.61 Vp, 1.22 Vpp, 5.7 dbm Input return loss: 25 db Gain 40 MHz: db/mhz Track/Hold gain change: 0.04 db Track/Hold glitch time constant: 1 ns Track/Hold glitch gain to input circuit: db 40 MHz: db Peak input signal: 1.13 Vp, 2.25 Vpp, 11 dbm Input return loss: 40 db Gain 40 MHz: db/mhz Track/Hold gain change: 0.04 db Track/Hold glitch time constant: 3 ns Track/Hold glitch gain to input circuit: db

6 The use of RF specified matching components is strongly recommended. Even if the operating frequency is 40 MHz, harmonics, glitches, and other disturbances will exist well into the GHz range and it s necessary that the circuit behaves as predicted at those frequencies if the ultimate performance is to be achieved. The anti-aliasing filter is in a package (Mini-Circuits GP731) which offers low-pass filtering with 18 different cutoff s between 36 and 500 MHz, or band-pass filtering with 18 different center frequencies from 75 to 650 MHz. Data is transferred to the carrier card at twice the ADC sample clock rate on 16 lines configured as 8 LVDS pairs, thus a full data word (14-bits, and clock) is provided to the carrier on every sample clock cycle. The pipeline latency of the ADC9255 is 12 cycles. Other functionality of the ADC (dither, power down, etc) is controlled via a serial bus from the carrier card. Noise and Jitter Performance The accuracy of the ADC is limited by the combination if its aperture jitter, internal noise, and the sampling clock jitter. The aperture jitter of the AD9255 is 70 fs which is near best in the field for high speed ADC s. The sum of the ADC s internal noise and aperture jitter can be surmised from its SINAD (signal to noise and distortion) level at a given input frequency. For the AD at 40 MHz, the SINAD is 78.0 dbfs which corresponds to an equivalent jitter of 354 fs, from which we see that the internal noise contribution, at 347 fs, is dominant. The 100 Hz to 1 MHz integrated noise of the Si570 with LVPECL outputs at MHz (from Table 8 of the datasheet) is about 200 fs. So the combination (in quadrature since we re adding RMS values) of the clock jitter (200 fs) and the ADC s total jitter (354 fs) is 406 fs. This corresponds to an effective SINAD of 76.8 db (or ENOB of 12.5) and represents the best performance we can expect from the circuit. 4 Output Channel The output channel is based around the MAX5890 DAC from Maxim. This is a low noise 14-bit 600 MSPS convertor with high dynamic range. The DAC output is AC (transformer) coupled with a frequency range of 5 to 450 MHz. The on-board reconstruction filter is the same as the ADC anti-aliasing filter with the same range of possible values. The appropriate filter should be chosen for the desired output frequency range. An amplifier boosts the output level to 2 Vpp (+10 dbm) into a 50Ω load with an return loss better than 30 db and an IP3 of 36 dbm. Data is fed from the carrier at the DAC sample clock rate on 28 lines configured as 14 LVDS pairs. The pipeline delay of this DAC is 5.5 cycles. The data must be synchronized with the clock in order to meet the recommended set-up and hold times (Figure 3 of the datasheet). This should be easily achieved by rotating the clock phase at a given frequency / data rate. The pipeline latency of the MAX 5890 is 5.5 clock cycles. The DAC (and output amp power supplies) can be powered down to reduce consumption/heating or noise during sensitive ADC measurements. 5 On Board OCXO s Two independent clocks are used to set the ADC and DAC sample rates. These are low jitter voltage controlled crystal oscillators, VCXO s (Si570 from Silicon Labs), whose frequency is digitally programmed over an I 2 C interface from the carrier board. Both clocks can feed their signal back to the carrier board which allows them to be used in a locked (PLL) configuration. The possibility of using the same OCXO with an additional analog control, Si571, was considered. The noise performance of the Si570 is better, but only for integrations that start below 10 khz which is the analog input bandwidth of the voltage control input of the Si571. It is assumed that the user will use the Si571 in a PLL that reduces the low frequency noise. Otherwise the noise of the two devices is the same above 10 khz.

7 If the Si570 is used the tuning is done in a digital manner which inherently has discreet steps. The 38 bit tuning word of the SI570 leads to a frequency resolution of 0.09 ppb. For a 100 MHz output frequency the worst case frequency error (0.045 ppb) is 4.5 mhz or 1.6 /sec. Thus the device will need to be continually reprogrammed, it s frequency dithered by one LSB, in order to maintain the correct output phase. This frequency dither will have the effect of increasing the effective phase noise. On the other hand the Si571 has a minimum control voltage slope of 33 ppm/v. Thus to achieve the same accuracy as the Si570 (0.09 ppb) the control voltage must set and maintained at a level of 2.7 nv. Noise at or above this level within the bandwidth of the loop will directly contribute to the added jitter, while an offset or drift, at this level, will constitute a frequency error. Maintaining noise and accuracy to a level of 3 nv is challenging in an analog environment, and very challenging (i.e. impossible) in a digital one. For this reason the Si570 was chosen to provide the on-board clocks. The Si570 has a programmable range of 10 MHz to 810 MHz. Each OCXO (with ECL fan-out) can be individually powered down to reduce power consumption/heating or noise during sensitive ADC measurements. 6 Crosspoint Switch and Output Data/Clock. There is a high performance (1.5 Gbps) low added jitter (1 ps 135 MHz) LVDS 4x4 crosspoint switch on board. The inputs are both OCXO s as well as two LVDS pairs from the carrier board. The outputs are two LVDS pairs back to the carrier board (on the dedicated CLK0,1_M2C connector pins) and two 2.5V CMOS/LVTTL level signals to the front panel co-ax connectors. The front panel outputs are capable of driving 50Ω loads with a 2V peak voltage in excess of 275 MHz (1Vpk in excess of 350 MHz). The LVDS pairs to the carrier card are frequency limited by the OCXO s at 810 MHz. The crosspoint switch is fully programmable through a serial (SMBus) bus allowing any input to go to any (or multiple) outputs. The switch must be powered up through the serial bus. 7 User Trigger or Clock I/O The user can provide or receive a TTL DC coupled level clock or trigger signal via a co-ax connector on the front panel. For inputs (user to card) the trigger accepts LVTTL signals with a 2V threshold. The input is high impedance (10µA peak current), TTL (5 V) tolerant, and can pass signals with a rate up to 400 MHz (Mbps). An internal 50Ω termination can be switched in to provide a well matched path for input triggers. For outputs (card to user) the trigger can operate at up to 250 Mbps at an output level of 8 ma. The internal 50Ω termination should not be used when the trigger is an output. The direction of the trigger is set by a LVTTL level signal from the carrier. A front panel LED indicates the chosen path (Yellow = Input, Green = Output).

8 8 Pin Allocations and Standards The following table summarizes the pin allocation and voltage standards for this card:

9 9 LPC Connector The following table summarizes the LPC connector mapping: