Analog Input Performance of VPX3-530

Transcription

1 TECHNOLOGY WHITE PAPER Analog Input Performance of VPX3-530 DEFENSE SOLUTIONS Table of Contents Introduction 1 Analog Input Architecture 2 AC Coupling to ADCs 2 ADC Modes 2 Dual Edge Sample Modes 3 Non-DES Mode Performance 4 DES Mode Performance 7 Overview of VPX Notes on Performance Measurements 11 Summary 11 Introduction Designers working on a mixed-signal application need to evaluate system components based on their fit with a specific situation; there are always technical tradeoffs to be considered. High resolution ADCs, particularly at high speeds, often exploit techniques such as ADC interleaving, but while the use of multiple ADCs is powerful, and common, there are potential issues to be addressed. For example, when an analog signal is split between two ADC there are challenges in terms of impedance matching, frequency response and matching the ADCs for phase and gain. All these will create artifacts such as frequency spurs which will limit overall performance by effectively rendering key criteria such as SFDR lower than may otherwise be expected. An evaluation of the VPX3-530 begins with the basic facts: it uses a pair of Texas Instrument ADC12D2000RF ADCs and a pair of Analog Devices AD9129 DACs. These are high performance, high speed devices and feature multiple modes. This white paper provides the typical (measured) performance of the analog inputs of the VPX3-530, what the advantages are of various modes and how well they compare with the formal device datasheets. The white paper then proceeds to give an insight to the true performance of the VPX3-530 in order for the developer to make reasoned decisions as to whether the VPX3-530 will meet application requirements and which configuration would be most effective for a particular application. Key questions addressed include: What modes and techniques does the VPX3-530 support? What performance can I expect? What are the tradeoffs between each mode? Info curtisswrightds.com ds@curtisswright.com Figure 1: Air and conduction-cooled VPX3-530 cards

2 Analog Input Architecture The ADC12D2000RF is a member of a family of ADC converter devices from Texas Instruments. This family includes 10 to 12-bit parts ranging from 1 to 2 GS/s. Each device includes two ADC on the same chip with more than one mode for either operating the part as a dual channel ADC, with a common sample rate, or a single ADC by interleaving the ADCs. When operated in interleaved mode, the input sample clock is used to sample one ADC on the rising clock edge and the other ADC on the falling clock edge. This gives rise to the interleaving modes being referred to DES (Dual Edge Sample) modes (see Figure 3). Conversely, operating the ADCs as independent channels and sampling off a common sample clock edge is referred to as non-des mode (see Figure 2). When using two-way interleaved ADCs, the sample instances must be 180 degrees out of phase so one ADC properly samples mid-way between the sample instances of the other ADC. Since the ADC12D2000RF uses both edges of the input sample clock to establish the sample instances, this means the clock input should be as close to a 50% duty cycle as possible otherwise false spurs and distortion will appear in the output data stream. The details of this are not discussed here, but just mentioned for reference. AC Coupling to ADCs The diagram to the right, see Figure 4, show the external balun configuration to support both the single-ended to differentia connectivity and the support of the external data feed for the DES modes. In each case, all the baluns are Mini Circuits TC1-1-13MG2+ components. Please refer to for more information. Please note, only general balun connectivity is shown and for clarity specific details of other components capacitor are not shown. ADC Modes The analog performance defined in the Texas Instrument s ADC12D2000RF is, by definition, for the device itself. When used on cards such as the VPX3-530, the performance will be factored by space limited design and the inclusion of necessary baluns, which for some performance parameters will modify the overall performance. The main effect, with analog input baluns will be the frequency roll-off as the effect of both the ADC and the balun are combined. Analog Input Analog Input Analog Input Figure 2: Non-DES mode Figure 3: DES mode ADC ADC I-Chan Q-Chan I-Chan Q-Chan Figure 4: External balun configurations for DES mode (above) and non-des mode (below) 2

3 DES (Dual Edge Sample) Modes In contrast to Non-DES, DES has several modes of operation. These modes include feeding in analog signals via the I-input channel, Q-input channel and letting the ADC device feed the analog input internally to both ADC channels or to accept the analog input separately, using an external signal splitter with an inverter on one of the clocks to one of the internal ADCs. These modes give rise to the naming conventions of the different modes. DESI and DESQ The most basic DES mode is DESI and DESQ (see Figure 5, below). The ADC devices route either the I or Q input to the internal ADCs and do not require an external signal splitter. Although the simplest DES mode, DES I and DES Q have the disadvantage of the highest insertion loss because a single ADC input is driving two ADC inputs, and therefore operates with half the overall impedance compared to a single independent channel. DESIQ Figure 5: DESI and DESQ modes DESIQ overcomes the insertion loss of DES I and DES Q by accepting inputs from the I and Q inputs and internally connecting the signals to ensure that there is a short trace to both internal ADC inputs and thereby better ensure that the inputs see the same signal (See Figure 6). However, the effect of having external splitters like this means that a common build which supports both non-des and DESIQ (or DESCLKIQ) is not possible. It is for this reason that the VPX3-530 can be provided in separate factory build options for non-des and DESIQ modes. DESIQ is an improvement over DES I and DES Q modes. Splitting the signal into two traces externally with each internal ADC being fed without an internal link, further improves insertion loss.; this mode, without internal connections, is DESCLKIQ. Figure 6: DESIQ mode DESCLKIQ DESCLKIQ mode relies on a more sophisticated external signal splitter with well-defined signal traces into the independently driven ADC inputs. See Figure 7. Consequently, the DESCLKIQ mode could offer the best analog input bandwidth. However, managing the tuning because there is no internal connection requires great care as generic settings are not possible and therefore this task is considered application dependent. Figure 7: DESCLKIQ mode 3

4 Non-DES Mode Performance 1 Non-DES is the simplest mode with independent signals fed into each of the ADC channels of the ADC12D2000RF devices. For the VPX3-530, each analog input is differential, but coupled via a balun for external single-ended inputs. Non-DES ENOB At 2GSPS, analog performance is relatively consistent for ENOB provided that the input level is at least 2dBm. These are typical performance characteristics. See Figure 8. At 498 MHz, the minimum performance as defined in the device datasheet is 8-bit ENOB. Figure 8: Non-DES ENOB performance with different analog input levels Each VPX3-530 has two ADC12D2000RF devices fitted, so account needs to be taken of both devices and the effects on all channels of layout. In general, the channel IO performance for ENOB correlates well and well within the typical-minimum margins of the device specification 3. See Figure 9 for an indication of channel to channel differences at a common analog input level (0dBm). Figure 9: Typical channel-to-channel variations for non-des ENOB 4

5 If the full 2GSPS sample rate for non-des is not required, then lower sample rates may improve performance 2. See Figure 10, below, for some indications, based on a single channel input sample being changed. As these variations are well within the typical/minimum performance levels for the ADC device, absolute performance cannot be guaranteed but it does indicate some latitude and possible advantage. Non-DES SNR Figure 10: Variation in ENOB performance vs input sample rate Similarly, SNR at a common input level is shown in Figure 11. At 498MHz, the device specifies a minimum performance expectation of 50.1 dbc which should be factored into the limits of the overall performance. Figure 11: Typical SNR between channels in non-des mode with common (0dBm) input level 5

6 Non-DES SINAD Non-DES full scale input bandwidth Figure 12: Non-DES mode SINAD The 3dB input bandwidth can be defined through the full-scale input measurements on the VPX The key difference when compared to the ADC12D2000RF datasheet is the inclusion of the balun feeding the ADC which has its own upper and lower frequency roll-offs. The combined effect of this is shown in Figure 13, below. Depending of the frequency range of interest, the upper 3dB roll off is ~1.6GHz or ~1.8GHz referenced to 100MHz lower frequency. However, the analog input signal can be seen well in the second Nyquist zone, but attenuated. Figure 13: Full scale input power in non-des mode 6

7 DES Mode Performance 1 The DES mode variant of the VPX3-530 is optimized for DESIQ, so the test results set out below are for this DES mode only. The VPX3-530 can be configured for DESCLKIQ, but the necessary application specific tuning means that any text results may not be representative and therefore no attempt has been made to include them here. DES mode, by definition, uses double-edge clocking. For the measured results set out below, the stated clock input should be double to read the net sample rate. For example, a 2GHz clock results in 4GSPS throughput. Please note: the measured performance parameter below are typical and will vary from board to board. DESIQ ENOB Typical performance from the VPX3-530 ENOB is consistent with the typical ADC12D2000RF expectations. See Figure 14 below. DESIQ SNR Figure 14: DESIQ ENOB (typ) Typical performance from the VPX3-530 SNR is consistent with the typical ADC12D2000RF expectations. See Figure 15 below. Figure 15: DESIQ SNR (typ) 7

8 DESIQ SFDR The typical performance measurements so far for the VPX3-530 indicate better than expected performance. These results should be considered better than typical and defer to the formal specifications outlined in the ADC12D2000RF datasheet for low frequencies. See Figure 16 below for measured results. DESIQ SINAD Figure 16: SFDR for DESIQ mode Typical performance from the VPX3-530 SINAD is consistent with the typical ADC12D2000RF expectations. See Figure 17 below. Figure 17: SINAD (typ) DESIQ mode 8

9 DESIQ full scaleinput bandwidth The 3dB input bandwidth can be defined through the full-scale input measurements on the VPX As with the Non-DES mode, the key difference when compared to the ADC12D2000RF datasheet for DESIQ mode is the inclusion of the balun feeding the ADC, which has its own upper and lower frequency roll-offs. The combined effect of this is shown in Figure 18, below. The analog input signal can be seen well in the second Nyquist zone, but attenuated. Figure 18: DESIQ mode full scale input 9

10 Overview of VPX3-530 Below, in Figure 19 and 20 are the two primary configurations of the VPX3-530 to support the ADC input modes, the 4x 2GSPS (non-des mode) and 2x 4GSPS (DES mode) options. Figure 19: Architecture of VPX3-530 showing non-des mode optimized ADC coupling RF CLK 0 RF CLK 1 ADC 0I ADC 0I DAC 0 DAC 1 Clock distribution/ control ADC/DAC clocks 4GSPS 12b ADC 4GSPS 12b ADC 5.6 GSPS 14b DAC 5.6 GSPS 14b DAC IO Sub-system FPGA Sub-system FLASH SDRAM Configuration Controller Virtex-7 VX690T FPGA Temperature Sensors Power Sensors Elapsed Time Indicator JTAG Header x8 HSS/PCIe 2/3 x8 GTH/HSS 5V/3V3 JTAG 1PPS x28 LVDS (1.8V) I/O 2x RS485 2x RS485 TRIG Out TRIG In LVPECL LVPECL x64 2/4GB DDR3 SDRAM x64 2/4GB DDR3 SDRAM Figure 20: Architecture of VPX3-530 showing DES mode optimized ADC coupling 10

11 Author Jeremy Banks, BSc (Hons) in Electronic and Electrical Engineering Product Marketing Manager Curtiss-Wright Defense Solutions Notes on Performance Measurements 1. For consistency with Texas Instruments datasheet for the ADC12D2000RF, Fs/2 spur was removed from all dynamic performance calculations. Tests were performed at room temperature. 2. These performance measurements were all made with ADC12D2000RF parts and not compared to VPX3-530 cards fitted with slower members of the same family. Such comparative tests results are not available. 3. Minimum performance parameters are specified in the ADC12D2000RF datasheet. The tests VPX3-530 cards did not find any components are the minimum limit, so card performance levels should be considered typical, but not guaranteed. Summary Once the baluns are factored in the VPX3-530 correlates well with the ADC12D2000RF specification. The ADC12D2000RF doesn t of course include this detail. In order to support the different modes of operation of the ADC12D2000RF, there are independent build options of the VPX Some modes, such as DESI and DESQ could be used on non-des mode (referred to as quad 2GSPS variants) optimized VPX3-530, but the bandwidth, due to insertion loss will be far poorer than specific DES mode configuration (referred to a Dual 4SPS variants). Having non-des and DES build variants provides optimal performance depending on the application s requirements and analog input bandwidth in particular. The overall analog bandwidth beyond the 3dB point degrades slowly, and depending on the application, has usable performance well beyond the first Nyquist zone even for 4GSPS DES mode. Attention is drawn to note 2 so as to compare performance of the VPX3-530 against the ADC12D2000RF datasheet. Learn More VPX3-530 Dual 4GSPS ADC Analog Input 2014 Curtiss-Wright. All rights reserved. Specifications are subject to change without notice. All trademarks are property of their respective owners. W