Analog-to-Digital Converter Survey & Analysis. Bob Walden. (310) Update: July 16,1999

Transcription

1 Analog-to-Digital Converter Survey & Analysis Update: July 16,1999 References: 1. R.H. Walden, Analog-to-digital converter survey and analysis, IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp , April R.H. Walden, Performance trends for analog-to-digital converters, IEEE Communications Magazine, vol. 37, no., pp , February HRL, LLC. ALL RIGHTS RESERVED

2 Outline Introduction ADC survey Characterization Performance Limits Architectures Trends Conclusions

3 What Does an Analog-to-digital Converter Do? It converts continuous-time signals to discrete-time binary-coded form. Two purposes are (1) to enable computer analysis of the signal, and, () to enable digital transmission of the signal. Some examples of continuous-time signals: speech, medical imaging, sonar, radar, electronic warfare, instrumentation, consumer electronics, telecommunications, The conversion can be thought of as a two-step process: sampling the input signal in time, usually at regularly-spaced intervals; f samp = 1/T, where T = sampling interval Example, for f samp = 1 gigasample per second, T = 1 ns. quantizing (or digitizing) the samples in amplitude, usually voltage. The full-scale input voltage is divided into N sub-ranges where N = the ADC s resolution (number of output leads). Example, for N = 1 bits, a 1-Volt full-scale range is divided into N = 496 levels. The size of the least-significant bit (LSB) is 1 V / N = 44 µv. 3

4 Analog-to-Digital Converter Data: Stated Resolution Over 17 converters represented Stated Resolution (Bits) module hybrid Si IC III-V IC SuperC state-of-the-art revised s-o-t-a HP(97) slope: -1 bit/octave Lucent(98) Maxim(5/99) HP(97) Hypres(6/99) 1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+1 1E+11 Sample Rate (Samples/s) 4

5 ADC Basics: Quantization Noise V FS Q Sinusoidal Signal analog waveform digitized waveform time quantization error -Q/ Randomized Signal T et Q t 1 () = ( ) T T Q/ Q = LSB = V FS / N N = ADC Resolution T = sampling interval 1 NP rms T Q t 1 Q ( ) = [ ( )] dt = T 1 VFS ( rms) SNR( db) = log ( NP ( rms) ) 1 VFS 1 = log 1( ) = 6. N VFS N 1 5

6 ADC Characterization Quasi-static tests Differential nonlinearity, DNL Integral nonlinearity, INL Dynamic tests Collect bits samples "at speed" and compute fast Fourier transform (FFT) Determine signal-to-noise ratio, spurious-free dynamic range, noise power ratio How do we count bits? Stated resolution = physical number of output leads (bits) Signal-to-noise ratio, SNR(dB) = 6.b eff b eff = SNR bits = (SNR(dB)-1.76)/6. determined for f sig < f samp / Spurious-free dynamic range, SFDR(dBc) SFDR bits = SFDR(dBc)/6 5 db 1 signal distortion noise floor frequency 6

7 Effective Resolution Bandwidth (ERBW) Measure SNR vs f sig, f samp ERBW is the signal frequency where the SNR is 3 db below the low frequency value If the ERBW is > f samp /, then we have a Nyquist converter In this presentation: quoted SNR values correspond to f sig << f samp / ADCs in this survey have.5f samp <~ ERBW <~.5f samp 7

8 Stated Resolution Contrasted with SNR and SFDR Stated Bits - SNR Bits 1-1 ideal - average difference = 1.47 bits E+4 1E+6 1E+8 1E+1 Stated Bits - SFDR Bits average difference = -.38 bits -5 1E+4 1E+6 1E+8 1E+1 Sample Rate (Samples/s) Sample Rate (Samples/s) 8

9 Spurious-Free Dynamic Range Data SFDR-bits = SFDR(dBc) / HP(97) SFDR bits Lucent(98) Maxim(5/99) 6 4 ADC data state-of-the-art revised s-o-t-a 1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+1 1E+11 Sample Rate (Samples/s) 9

10 ADC Performance Limitations: Circuit Noise Equivalent input-referred thermal noise <v n > = 4kTR eff f samp / R eff includes contributions due to thermal noise, shot noise, flicker noise, and input-referred noise terms thermal noise contribution includes the signal source resistance maximum resolution (+/-.5 LSB) V 1 pp Bmax = log ( ) 1 6kTR f eff samp in this presentation, V pp = 1 V 1

11 ADC Performance Limitations: Comparator Ambiguity Comparator Signal τ reg 1 f T track recovery voltage regeneration Analog Signal Sample Mode time Hold Mode Sample Mode B ambiguity π ft = f samp 11

12 ADC Performance Limitations: Aperture Uncertainty Aperture jitter τ a uncertainty in sampling time varies from sample-to-sample broadband noise on sampling clock circuit noise power-line noise digital feedthrough noise phase noise on sampling clock phase noise on input signal system problem: on-chip & off-chip noise sources (having a clean, stable clock may not be enough) maximum resolution (+/-.5 LSB): B aperture signal clock = log ( ) 1 3πf τ samp a 1

13 ADC Performance Limitations: Heisenberg Uncertainty Principal T/ LSB/ LSB T T E =, t = R 1 LSB T E t = h R 4 1 fsamp = T LSB = V V FS = 1V FS N R = 5Ω h R = N VFS / fsamp = hr eg.., 1 bits@ 84 GSPS τ ah, = π N 1 f samp =. 93 fs 15 13

14 ADC Performance Limitations (updated 7/16/99) Basis: Signal-to-Noise Ratio thermal aperture Heisenberg ambiguity SNR bits ADC data aperture (1 ps) aperture (.5 ps) aperture (. ps) regen (5 GHz) regen (5 GHz) thermal (5 ohms) thermal ( ohms) Heisenberg (.9fs) HP(97) Lucent(98) Maxim(5/99) Hypres(6/99) HP(97) 1E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+1 1E+11 Sample Rate (Samples/s) 14

15 ADC Power Dissipation Power consumption varies by roughly six orders of magnitude. 5 P diss (dbm) P diss (dbm) Log(fsamp) SNR bits P diss (dbm) Average ~ 3 dbm 15

16 ADC Figure of Merit updated 7/16/99 Number of ADCs median = 1.14 x 1 1 LSBs-Hz/W mean = 7.79 x 1 1 LSBs-Hz/W F = SNRbits x f samp / P dis 1.E+1 1.E E+11.8E E E E E E+11 8.E E+11 1.E+1 1.1E+1 1.E+1 Figure of Merit, F 16

17 6 ADC Figure of Merit - p Number of ADCs F = SNRbits x f samp / P dis 8.8 SNRbits, 15 MSPS pipelined [8] 6 SNRbits, 1 GSPS 1.3 SNRbits, SuperC w/o refrig. 5 MSPS 15. SNRbits, 15.7 SNRbits, 44 ksps (6.6E13) [34] folded [5] 1.5 MSPS Σ w/o DF [3] Σ w/o DF [31] 7.8 SNRbits, 11.3 SNRbits, 1.5 SNRbits, 4 ksps 65 MSPS folded [1] 65 MSPS AD664 [9] 15.5 SNRbits, 5 ksps Σ w/o DF [33] Σ w/o DF [3] 13.8 SNRbits, 5 MSPS mean 9.5 SNRbits, pipelined [6] MSPS pipelined [7] 1.E+1 1.E E+11.8E E E E E E+11 8.E E+11 1.E+1 1.1E+1 1.E+1 Figure of Merit, F 17

18 High Performance ADCs High Figure of Merit: 13.8 SNRbits, 5. MSPS; 4-stage, calibrating; Kwak et al., et al., SNRbits, 4 ksps; Σ, OSR = 5; Chen & Leung, SNRbits, MSPS; pipelined, digital correction; Cho & Gray, SNRbits, 15 MSPS; pipelined, interpolating; Kusumoto et al., SNRbits, 5 MSPS; folded flash, interpolating; Vorenkamp et al., 97 State-of the Art Performances (P = SNRbits x f samp ): 6.6 SNRbits, 4. GSPS; time interleaved, 4W; Schiller & Byrne, SNRbits,. GSPS; folded flash; Nary et al., SNRbits, 1. GSPS; flash; Maxim Max14, SNRbits, 1.8 GSPS; flash; Wong et al., SNRbits,. GSPS; superconducting folded-flash; Hypres, 99 High Spur-Free Dynamic Range 18.3 SFDRbits, MSPS; dithered, HP E1437A, SFDRbits, 65 MSPS; dithered, Lucent CSP115A, 98 Flexible: 6 MHz IF, 4 GHz clock, nd order bandpass Σ, Raghavan, et al., SNR 63 MHz bw 14.9 SNR 366 khz bw 18

19 High Performance ADC Architectures dithering improves SFDR Example: introduce dithering by addition of pseudorandom noise to an ideal 11-bit ADC SFDR increases SNR decreases optimum PRN level ~ 1/ LSB 4 No dither input = -6. db SNR = 68. db SFDR = 9.5 dbc 4 Dither enabled input = -6. db SNR = 65.6 db SFDR = 1. dbc f sigj f clk f sigj f clk 19

20 High Performance ADC Architectures moderate sample-rate, high resolution Delta sigma ( Σ): a combination of oversampling and feedback leads to suppression of quantization noise at low-frequency end of spectrum. analog front-end contains a small number of low-precision components digital back-end contains most of the complexity most popular configuration is a cascade of first and/or second order modulators requires ultra high speed IC technology for RF applications bandpass modulators add new dimensions tunable center frequency tunable bandwidth reduce number of downconversions bandpass digital filtering replaces analog filtering functions (better blocking of interferers)

21 Bandpass Delta Sigma Converters x(z) resonators Σ H(z) ADC e(z) y( z) N DSP / DAC db wideband y(z) = {z -1 H(z)x(z) + e(z)} / {1 + z -1 H(z)} Resonators determine modulator frequency response and are tunable Sample rate of modulator is sample rate of the quantizer (ADC) DSP is a complex digital circuit and performs bandpass filtering and downconversion Sample (Nyquist) rate of ADC is set by DSP Number, N, of output leads limits ADC resolution frequency (Hz) narrowband tunable notch frequencies 1

22 Progress in Performance Improvement Over Time: SNR SNR bits ~ 1 1/ bits in 9 years ~ 1 1/ bits in 7 years < E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+1 1E+11 Sample Rate (Samples/s)

23 Progress in Performance Improvement Over Time: SFDR ~ bits in 9 years SFDR bits < E+4 1E+5 1E+6 1E+7 1E+8 1E+9 1E+1 1E+11 Sample Rate (Samples/s)

24 ADC Performance Trend using Derived Aperture Jitter 1.E-11 fit log (best data) Derive τ a values from SNR data: derived aperture jitter (s) 1.E-1 1.E-13 best data fit log (best data), normalized to best result τ a = 11 fs (required for 1 MSPS) τ a = SNRbits 1 = 3 π P 3 π f samp current best ~.5 ps trend shows very gradual improvement actual progress is sporadic 1.E year 4

25 ADC Technology Comparison Conclusions ADC Survey Over 17 converters: experimental and commercial SNR bits: ranged from to 3.5 bits below stated resolution SFDR bits: ranged from 4 bits below to 4.5 bits above stated resolution Performance limitations: aperture uncertainty (?) (~ 1 ps), IC technology speed (~ 5-8 GHz) Figure of merit: F = (SNR bits) x f samp / P diss (mean = 7.8 x 1 1 LSBs-Hz/W) High performance architectures Time interleaved Folded, interpolating Pipelined Dithered (high SFDR) Delta sigma (including bandpass) Relatively little improvement in ADC performance during recent years (P = (SNR bits) x f samp < 4.96 x 1 11 LSBs - Hz) 5