Performance Improvement of Delta-Sigma ADC/DAC/TDC Using Digital Technique

Transcription

1 群馬大学 小林研究室 S38-1 Data Converters 15:45-16:15 PM Nov. 2, 2018 (Fri) Performance mprovement of Delta-Sigma ADC/DAC/TDC Using Digital Technique Haruo Kobayashi J.-L. Wei, M. Murakami, J. Kojima, N. Kushita, Y. Du, J. Wang Gunma University, Japan Gunma University Kobayashi Lab

2 Contents Objective of This Paper What is DWA? LP, HP DWA Multi-Bandpass DWA Multi-Bandpass Complex DWA Second-Order DWA Application to Multi-bit ΔΣ TDC Conclusion 2/55

3 Contents Objective of This Paper What is DWA? LP, HP DWA Multi-Bandpass DWA Multi-Bandpass Complex DWA Second-Order DWA Application to Multi-bit ΔΣ TDC Conclusion 3/55

4 Objective of This Paper Review the research results of authors group in the area of DWA: Data Weighted Averaging. ADC/ DAC performance improvement with simple digital techniques Consider their application to TDC Consider to unify the DWA algorithms and establish their design methodology. 4/55

5 Contents Objective of This Paper What is DWA? LP, HP DWA Multi-Bandpass DWA Multi-Bandpass Complex DWA Second-Order DWA Application to Multi-bit ΔΣ TDC Conclusion 5/55

6 Calibration Techniques Classification ADC/DAC/TDC digital calibration techniques prevail in nano-cmos era. Error Correction - No measurement of errors - Redundancy usage Self-Calibration - Error measurement - Compensation - Reference Voltage Current Time (frequency) Linearity 6/55

7 Power Power Power Power DWA Techniques Error Correction - No measurement of errors - Redundancy usage Time averaging of errors Spectrum shaping of errors DWA: Data Weighted Averaging DEM: Dynamic Element Matching Signal Errors W/O DWA Fs/2 LP DWA Fs/2 Fs/2 BP DWA Fs/2 HP DWA 7/55

8 Segment DAC with Redundancy Digital input = 4 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 R 4 Vout 4R Multiple realization configurations T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 Vout 4 R 4R T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 Vout 4 R 4R 8/55

9 Unit Cell Mismatches Current mismatches e15, e14,,e1 spectrum shaping by cell selection order e15 T15 e14 e13 e12 e11 e10 e9 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 out1=4[e4e3e2e1] e8 e7 R e6 e5 e4 e3 e2 e1 Vout 4Rout1 DWA algorithm No measurement of e15, e14,,e1 e15 T15 e14 e13 e12 e11 e10 e9 e8 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 out2=4[e8e7e6e5] e7 R e6 e5 e4 e3 e2 e1 Vout 4Rout2 e15 T15 e14 e13 e12 e11 e10 e8 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 out3=4[e14e13e12e11] e9 e7 R e6 e5 e4 e3 e2 e1 Vout 4Rout3 9/55

10 ΔΣ Modulation and DWA ntegrator ADC Differentiator Vin 1 Σ Gain DAC 1-z -1 Vs Vad Eq δ Nonlinearity Δ Gain Vout Digital Filter 1-z -1 Vd Vout f BW Freq Freq Power Power Power Power Power Freq Freq Freq Freq Freq Vout(z) = Vin(z) (1 z -1 ) δ(z) DAC nonlinearity δ(z) is first-order noise-shaped. 10/55

11 ΔΣ Modulation and DWA DC input ntegrator ADC Differentiator Vin 1 Σ Gain nfinite δ DAC 1-z -1 Vs Vad Eq Nonlinearity Δ Gain Vout Digital Filter 1-z -1 Vd Vout f BW Freq Freq Power Power Power Power Power Freq Freq Freq Freq Freq This configuration can NOT be implemented! 11/55

12 Time Time Equivalent Operation Using DWA to ΔΣ Modulation DAC input Normal DAC DAC DAC output DAC input DWA DAC DAC pointer DAC output Digital nput Current Cell Digital nput Current Cell nfinite is equivalently realized with wrap-around 12/56

13 DWA Operation is a fun! 13/56

14 Contents Objective of This Presentation What is DWA? LP, HP DWA Multi-Bandpass DWA Multi-Bandpass Complex DWA Second-Order DWA Application to Multi-bit ΔΣ TDC Conclusion LP: Low Pass HP: High Pass 14/55

15 power LP ΔΣAD Modulator Analog input X(z) - H(z) Filter Quantization noise ADC E(z) Digital output Y(z) Y(z)= STF NTF H(z) 1H(z) X(z) 1 1H(z) E(z) DAC Output power spectrum Signal band :E :ΔΣADC noise 1 0 f 15/56

16 Power Power Power Varieties of ΔΣAD Modulators X(z) H(z) Y(z) LP ADC - DAC Fs/2 X(z) - H(z) HP ADC Y(z) DAC Fs/2 X(z) - H(z) BP ADC Y(z) DAC Fs/2 16/56

17 Analog Multi-bit DAC Nonlinearity Ain Filter ADC Dout Multi-bit DAC Nonlinearity Digital X(z) H(Z) E(z) Y(z) :Single-bit Output :Multi-bit Output δ(z) H ( z) 1 Y ( z) z 1 H ( z) 1 H ( z) X ( z) ( z) E( ) δ(z) is NOT noise-shaped 17/56

18 Why Multi-bit ADC/DAC inside ΔΣ AD Modulator? Single-Bit Multi-Bit - High slew-rate of opamp Large power - Low slew-rate of opamp Small power - Problem: Multi-bit DAC nonlinearity 18

19 Time R Unit Cell Mismatches Segment DAC Current Cell Mismatch (e0,e2,e3, e7) DAC nonlinearity S S 0 1 S S 2 7 Errors of specific current cells are accumulated nput Data Current Cell Ⅰe 0 Ⅰe 1 Ⅰe 2 Ⅰe /56

20 Power DAC input Equivalent LP DWA Algorithm Z -1 DAC nonlinearity δ(z) DAC Z -1 - DAC output Digital integration Analog differentiation Signal ntegration x Differentiation=Flat DAC Nonlinearity Differentiation (High Pass) DAC nonlinearity effects at DAC output 0 Fs/2 f 20/56

21 Time LP DWA Algorithm Realization DAC nonlinearity δ(z) DAC input Z -1 DAC Z -1 - DAC output Digital integration Analog differentiation e 6 e 5 S 6 - e 0 e 7 S 5 S 7 ON ON ON S 0 ON ON R Vdd ON S 4 S 3 S 1 e 1 ON S 2 ON e 3 e 4 e 2 Vout DAC input H(z)=1/(1-Z -1 ) Current Cell /56

22 Power Let s Consider HP DWA Algorithm DAC nonlinearity δ(z) DAC input - Z -1 DAC Z -1 DAC output Digital differentiation Analog integration Signal Differentiation x ntegration=flat DAC Nonlinearity ntegration(low Pass) DAC nonlinearity effects at DAC output f 0 Fs/2 22/56

23 Time HP DWA Algorithm Realization DAC nonlinearity δ(z) DAC input - Z -1 DAC Z -1 DAC output Digital differentiation Analog integration e 6 e 5 S 6 - e 0 e 7 S 5 S 7 ON ON ON Vdd S 0 ON ON ON R ON S 4 S 3 S 1 e 1 ON S 2 e 3 e 4 e 2 Vout nput Data H(z)=1/(1Z -1 ) Current Cell Back and forth 23/56

24 Contents Objective of This Presentation What is DWA? LP, HP DWA Multi-Bandpass DWA Multi-Bandpass Complex DWA Second-Order DWA Application to Multi-bit ΔΣ TDC Conclusion [1] A. Motozawa, H. Kobayashi, et. al., "Multi-BP ΔΣ Modulation Techniques and Their Applications", ECE Tran, J90-C(Feb. 2007). 24/55

25 Power Power Type DWA N pointers Multi-Bandpass DWA DAC nonlinearity shaping N-channel interleave of LP DWA algorithm 0 1/N 2/N 3/N 4/N f Type DWA N pointers N-channel interleave DAC nonlinearity shaping of HP DWA algorithm 1/2N 3/2N 5/2N 7/2N 25/56 f

26 Time Time LP Algorithm LP Pointer TypeⅠ LP Multi-BP Multi-BP Algorithm (LPF) N=4 LP Pointer LP Pointer LP Pointer Digital nput LP Pointer H(z)=1/(1-Z -1 ) H(z)=1/(1-Z -4 ) Current Cell Digital nput Current Cell /56

27 Time nput data TypeⅡ HP BP Multi-BP HP Algorithm BP Algorithm Multi-BP Algorithm N=2 N=4 HP Pointer HP Pointer HP Pointer H(z)=1/(1Z -1 ) Back and forth Current cell HP Pointer HP Pointer HP Pointer HP Pointer H(z)=1/(1Z -2 ) H(z)=1/(1Z -4 ) /56

28 Multi-BP Type Ⅱ N=4 H(z) H(z) E(z) X(z) - Multi Bandpass Filter Multi Bandpass Filter ADC Y(z) Type Ⅱ DWA DAC H(z) -Z -4 1Z -4 STF = -Z -4 NTF = (1Z -4 ) 2 Signal Bands 1/8, 3/8 X Fs 28/56

29 Multi-BP Type Ⅱ N=4 Simulation Results w/o DWA DAC w/ DWA DAC deal DAC w/o DWA DAC w/ DWA DAC deal DAC Slope 15dB/Oct Multi-BP DWA algorithm is effective 29/56

30 Contents Research Objective What is DWA? LP, HP DWA Multi-Bandpass DWA Multi-Bandpass Complex DWA Second-Order DWA Application to Multi-bit ΔΣ TDC Conclusion [1] M. Murakami, H. Kobayashi, et.al., "-Q Signal Generation Techniques for Communication C Testing and ATE Systems", EEE nternational Test Conference (Nov. 2016). [2] H. San, H. Kobayashi, et. al., "A Second-Order Multi-bit Complex Bandpass ΔΣ AD Modulator With, Q Dynamic Matching and DWA Algorithm", ECE Trans. Electron, (June 2007). 30/55

31 Necessity of,q signal RF analog front-end of Receiver C RF cos(ωlot) mixer n-phase ADC DSP -sin(ωlot) Quadrature-phase Need testing!

32 Necessity of Multi-Tone Signal Linearity testing of Mixer Up/Down converter Radio communication system, etc. Need! Multi-tone signal Noise Power Ratio nput Output DUT (NPR) NPR Distortion by DUT ω DUT:Device Under Test ω

33 2nd-order Complex Multi-BP ΔΣ DAC Output spectrum Single-band Multi-band

34 Principle of Complex BP Noise Shape Complex resonator Quantization noises Power Signal Transfer Function = 1 1 ω 0 Noise Transfer Function = 0

35 Power Complex Resonator Output spectrum pole pole pole pole pole -0.5 ωin / ωs 0.5 Single-band -0.5 ωin / ωs 0.5 Multi-band

36 Power Complex Resonator Asymmetric Asymmetric Output spectrum pole pole pole pole pole -0.5 ωin / ωs 0.5 Single-band -0.5 ωin / ωs 0.5 Multi-band

37 Equivalent Circuit of Complex DWA Complex resonator δ Complex notch filter in DAC1 out z - N z - N Qin z - N δq DAC2 z - N Qout δ, δq affected by only complex notch DAC input can be Can t be realized directly

38 Equivalent Circuit mplementation in out Qin Qout Attach pointers Exchange upper-path and lower-path every N clock Complex DWA is realized.

39 DAC nput DAC nput Complex Multi-Bandpass DWA Algorithm N = 4(four zero points) DAC1 (LP operation) in Qin DAC2 (HP operation) in Qin

40 Simulation Result ~deal Linear DAC~

41 Simulation Result ~Actual Non-Linear DAC~ δ δq Notches filled with noise

42 Simulation Result ~Actual Non-Linear DAC DWA~ δ DWA δq Notches filled with noise

43 Simulation Result ~Actual Non-Linear DAC DWA~ δ DWA DWA δq DWA Notches filled with noise Steep Notches

44 Contents Research Objective What is DWA? LP, HP DWA Multi-Bandpass DWA Multi-Bandpass Complex DWA Second-Order DWA Application to Multi-bit ΔΣ TDC Conclusion [1] H. Hagiwara, H. Kobayashi, et. al., DA Converter Circuit Provided with DA Converter of Segmented Switched Capacitor Type, US Patent Application, Pub. No.: US 2005/ A1 (Dec. 29, 2005). 44/55

45 2 nd -order DWA X Y z =X z (1 z 1 ) 2 δ(z) K N O P M L DAC δ Y 1/z 1/z 1/z 1/z 2 integrators 2 differentiators 2 nd -order DWA is more effective But its circuit/operation become complicated 45/55

46 Contents Research Objective What is DWA? LP, HP DWA Multi-Bandpass DWA Multi-Bandpass Complex DWA Second-Order DWA Application to Multi-bit ΔΣ TDC Conclusion [1] T. Chujo, H. Kobayashi, et. al., Timing Measurement BOST With Multi-bit Delta-Sigma TDC, 20th EEE nternational Mixed-Signal Testing Workshop (June 2015). 46/55

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49 ΔΣTDC Configuration [1] T. Chujo, H. Kobayashi, "Timing Measurement BOST With Multi-bit Delta-Sigma TDC, EEE MSTW (June 2015). [2] Y. Osawa, H. Kobayashi, Phase Noise Measurement Techniques Using Delta-Sigma TDC, EEE MS3TW (Sept. 2014). 49/55

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51 CLK1 CLK2 Multi-bit ΔΣ TDC with DWA For short measurement time: Delay Line 1 Delay Line 2 Delay Line 7 M U X M U X M U X M M 位相 t U t U t PD 積分器 X X 比較器 Dt 1 M Dt 2 M Dt 7 M U U U X X X M U X Phase Detector CLK Flash ADC Dout 7 DWA 7 DWA: Data Weighted Averaging DSP algorithm of compensation for mismatches among delays. 51/55

52 Measured Result TDC output # of 1 s TDC output # of 1 s T [ns] T [ns] ntegral Non-linearity 10,000 TDC output data are measured. T [ns] Analog FPGA mplementation 52/55

53 Contents Research Objective What is DWA? LP, HP DWA Multi-Band DWA Multi-Band Complex DWA Second-Order DWA Application to Multi-bit ΔΣ TDC Conclusion 53/55

54 Conclusion Spectrum shaping of errors is possible with DWA algorithms. Their hardware implementation is simple. So far, DWA algorithm derivation is based on mathematical intuition of the researcher as well as simulation. There are no systematic or theoretical methods. There are still possibilities of new DWA algorithms. 54/55

55 Final Statement Mathematics is the alphabet with which God has written the Universe. Galileo Galilei Mathematics is the alphabet with which the circuit designer writes his/her new idea. 55/55

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57 Contents Research Objective What is DWA? LP, HP DWA Multi-Band DWA Multi-Band Complex DWA Second-Order DWA Application to Multi-bit ΔΣ TDC Digital Dither for ΔΣ DAC Conclusion [1] J. Kojima, H. Kobayashi, et. al., Limit Cycle Suppression Technique Using Digital Dither in Delta Sigma DA Modulator, EEE CSCT (Nov. 2016). [2] J. Wei, H. Kobayashi, et. al., Limit Cycle Suppression Technique Using Random Signal in Delta-Sigma DA Modulator, EEE CSCT (Nov. 2018). 57/55

58 ΔΣ DA Converter Digital input ntegrator Quantizer 1bit DAC LPF Analogo utput Feedback ΔΣ Modulator Digital Analog High linear, High resolution <Usage> Measurement Audio 58/56

59 Merits & Demerits of ΔΣ DAC Digital input Modulator output 1bit Analog DAC LPF Merit Mostly digital circuit High linear & high resolution for low frequency signal generation Limit cycle Analog output Demerit Limit cycle problem for small input Due to modulator nonlinearity by quantizer 59/56

60 Adding Dither at nput Adding random signal to digital input Random signal Digital input Analog output Analog LPF Drawbacks nput range sacrifice Random signal has to be out of signal band difficult to generate 60/56

61 Our Approach Digital input Digital dither signal 1bit DAC Analog output Analog LPF Limit cycle reduction with digital dither signal Limit cycle Smooth! Stair 61/56

62 Proposed Circuit Dither input Digital input Modulator output 1bit DAC XOR LPF Analog output < Features > 1 1-bit output 2 Digital dither NOT affect output signal, thanks to feedback Digital signal 1 reverses comparator output with XOR 62/56

63 10-bit case Simulation Results Sine wave Center value: Amplitude:0.094 DC = 0.1 Conventional Proposed 63/56

64 Another Configuration LP modulator BP modulator w/o dither w/ dither 64/55

65 Modulator Operation Without dither With dither DC nput Dither signal Time domain Period Frequency domain DC nput Orders of 0 and 1 -> different Total numbers of 1 s -> the same DC signal power -> the same Linear Not Periodic Diffusion Noise 65/56

66 10-bit case SFDR Comparison Amplitude Digital dither Center value Varying DC input With dither Without dither SFDR improvement by more than 10dB 66/56

67 10-bit case DC = 0.1 SFDR = SFDR (Spurious Free Dynamic Range) Signal Power Maximum Harmonics Power SFDR = 5.4 db < 22.9 db Conventional Signal Power Proposed Maximum Harmonics Power 67/56

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69 Power Type Ⅰ N=8 Multi-BP AD Modulator X(z) - H(z) Multi Bandpass Filter H(z) Multi Bandpass Filter E(z) ADC Y(z) TypeⅠ DAC H(z) Z -8 1-Z -8 : input signal noise 0 1/8 1/4 3/8 1/2 Fin/fs STF = Z -8 NTF = (1-Z -8 ) 2 Signal Bands : 0, 1/8, 1/4, 3/8,1/2 x Fs 69/56

70 Type Ⅰ N=8 Multi-BP AD Modulator Simulation Results 15dB/Oct Modulator operation is confirmed. 70/56

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72 Conclusion Spectrum shaping of errors is possible with DWA algorithms. Their hardware implementation is simple. The algorithm derivation is based on mathematical intuition of the researcher as well as simulation. There are no systematic or theoretical methods. There are till possibilities of new algorithm. Dither adding at the comparator is effective. 72/55