DAC Architecture Comparison for SFDR Improvement

Transcription

1 DAC Architecture Comparison for SFDR Improvement ETT Shaiful Nizam Mohyar*, H. Kobayashi, Gunma University, Japan Universiti Malaysia Perlis, Malaysia Gunma University, Japan

2 Outline Introduction Investigated DAC Architecture Code Selection Technique Simulation Result Conclusion Gunma University, Japan 2

3 Outline Introduction Investigated DAC Architecture Code Selection Technique Simulation Result Conclusion Gunma University, Japan 3

4 Background Telecommunication devices Mobile phones, wireless modems & avionics High-speed, high-accuracy DAC!!! Transmitter Introduction DAC Digital-to-Analog Converter Gunma University, Japan SFDR Spurious Free Dynamic Range

5 Motivation & Objective Motivation Design high SFDR DAC with digital rich configuration Objective Reduce interference due to circuit non-idealities Current source mismatch Approach Different DAC architectures & code selection technique 5

6 Spurious Free Dynamic Range (SFDR) Degradation sources Current source mismatch Output impedance change Imperfect switch Temporal disturbance Gunma University, Japan 6

7 Investigated Method Method Different DAC architecture (Intrinsic redundancy) Binary weighted DAC Unary weighted DAC Fibonacci sequence based DAC Code selection based on Look-Up Table (LUT)) Fix (Counter) Random (Randomizer) Combination Dynamic non-linearity improvement SFDR Spurious Free Dynamic Range Gunma University, Japan 7

8 Current-steering DAC (CS DAC) High-speed Easy to integrate High-resolution Low-power Small chip area Unit cell Gunma University, Japan 8

9 CS DAC limitation Transistor mismatch Current source mismatch Source of timing errors Mismatch among current cells Causing DAC static & dynamic non-linearity Better transistor matching Big size Power loss Laid out close to each other Complicated CS DAC Current-steering DAC Gunma University, Japan 9

10 Current-steering DAC architecture (1) Binary Small silicon area High sampling speed Large glitch energy No redundancy Unary / Thermometer-coded (TC) Small glitch energy High sampling speed Redundancy Large silicon area CS DAC Current-steering DAC Gunma University, Japan 10

11 Current-steering DAC architecture (2) Segmented Balanced performance Complex CS DAC Current-steering DAC Gunma University, Japan 11

12 Analog output Analog output current, A current, A Current Source Mismatch Ideal case Process Variation Mismatch case current cell current cell DAC nonlinearity!!! Digital input Digital input Gunma University, Japan 12

13 Nonlinearity & SFDR degradation Ideal Mismatch CS Mismatch Nonlinearity SFDR degradation CS Current Source SFDR Spurious Free Dynamic Range Gunma University, Japan 13

14 Outline Introduction Investigated DAC Architecture Code Selection Technique Simulation Result Conclusion Gunma University, Japan 14

15 Fibonacci sequence Generally Ratio lim n Fibonacci sequence F 0 = 0; F 1 = 1; F 2 = F 0 + F 1 F n+2 = F n + F n+1 n 0 F n = 0, 1, 1, 2, 3, 5, 8, 13, F n F n Unary < Fibonacci < Binary Gunma University, Japan 15

16 Redundancy Step occupied silicon area Code combination output optimization Binary < Fibonacci < Unary (Area) ( Area & Redundancy) (Redundancy) Gunma University, Japan 16

17 Investigated DAC Fibonacci sequence based DAC Small silicon area Redundancy Large glitch energy Gunma University, Japan 17

18 Outline Introduction Investigated DAC Architecture Code Selection Technique Simulation Result Conclusion Gunma University, Japan 18

19 1. Fixed Counter (Fibonacci) DSP Digital Signal Processing Gunma University, Japan 19

20 Digital Input Digital Input Digital Input Decoder (LUT) Column Column Column 1 Generate all possible code combinations 2 Decide number of column 3 Add empty column by repeating existed code LUT Look-Up Table Gunma University, Japan 20

21 [SW4,SW3,SW2,SW1] = [1,1,1,1] = [1,0,0,1] = [0,0,0,1] [1, [0, 1, 0, 1, 0, 1] Operational (Fix) Clock : (Digital input = 7) 4) 1) Output Input DSP [b2,b1,b0] Decoder = address [0,0,1] [1,1,1] [1,0,0] switch [SW4,SW3,SW2,SW1] [b2,b1,b0 2b-Counter,q1,q0] [q1,q0] = [0,0,1,1,0] [1,1,1,0,0] [1,0,0,0,1] = [0,0] [0,1] [1,0] = [0,0,0,1] [1,1,1,1] [1,0,0,1] [b2,b1,b0] = [1,1,1] [1,0,0] [0,0,1] [b2,b1,b0,q1,q0] [b2,b1,b0,q1,q0] = [0,0,1,1,0] [b2,b1,b0,q1,q0] = [1,0,0,0,1] = [1,1,1,0,0] [q1,q0] = [0,0] [0,1] [1,0] Gunma University, Japan 21

22 2. Randomizer (Fibonacci) Gunma University, Japan 22

23 [SW4,SW3,SW2,SW1] = [1,1,1,1] [SW4,SW3,SW2,SW1] = [1,0,0,1] [SW4,SW3,SW2,SW1] = [0,0,1,0] [1, [0, 1, 0, 1, 1, 1, 1] 0] Operational (Random) Clock : (Digital input = 7) 4) 1) Output Input DSP [b2,b1,b0] Decoder = address [0,0,1] [1,1,1] [1,0,0] switch [SW4,SW3,SW2,SW1] [b2,b1,b0 2b-Randomizer,q1,q0] [q1,q0] = [0,0,1,0,1] [1,1,1,1,0] [1,0,0,0,0] = [1,0] [0,0] [0,1] = [0,1,1,1] [0,0,1,0] [1,1,1,1] [b2,b1,b0] = [1,0,0] [1,1,1] [0,0,1] [b2,b1,b0,q1,q0] = [1,1,1,1,0] [b2,b1,b0,q1,q0] [b2,b1,b0,q1,q0] = [0,0,1,0,1] = [1,0,0,0,0] [q1,q0] = [0,0] [1,1] [1,0] Gunma University, Japan 23

24 Outline Introduction Investigated DAC Architecture Code Selection Technique Simulation Result Conclusion Gunma University, Japan 24

25 SFDR Performance (a) Ideal 83.4 db (b) Unary 80.2 db 10-bit fin = 400MHz, fs = 2GHz, mismatch: 10%, min:-0.05, max:0.05 (c) Binary 76.9 db (d) Fibonacci (fix) 75.7 db (e) Fibonacci (random) 75.8 db Gunma University, Japan 25

26 Number of Column SFDR Performance fin = GHz, fs = 2GHz, 10-bit mismatch: 20%, min:-0.1, max: dB 68.7dB 68.8dB Unary DAC Fibonacci DAC (random) Fibonacci DAC (fix) 67.3dB +2dB Binary DAC Gunma University, Japan 26

27 Outline Introduction Investigated DAC Architecture Code Selection Technique Simulation Result Conclusion Gunma University, Japan 27

28 Conclusion SFDR performance (4 columns selection) Unary > Binary > Fibonacci Fibonacci (Fix & Random) Binary SFDR performance ( > 4 columns selection) Fibonacci (Fix & Random) > Binary +2dB Unary > Fibonacci > Binary Future work Need more proper code arrangement Gunma University, Japan 28

29 Thank you very much for your kindly attention Gunma University, Japan 29

30 Q & A Q: To compare the redundancy, why not compared with other existed architectures which also use redundancy rather than compare with conventional binary architecture? Gunma University, Japan 30