MOS Transistor Mismatch for High Accuracy Applications

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1 MOS Transistor Mismatch for High Accuracy Applications G. Van der Plas, J. Vandenbussche, A. Van den Bosch, M.Steyaert, W. Sansen and G. Gielen * Katholieke Universiteit Leuven, Dept. of Electrical Engineering, ESAT-MICAS Kardinaal Mercierlaan 94, B-31 Heverlee, Belgium geert.vanderplas@esat.kuleuven.ac.be Abstract In this paper the matching behaviour of MOS transistors is analyzed for the realization of an intrinsic accuracy 14 bit current steering D/A converter. It is well known that the area of a MOS transistor is inversely proportional to the mismatch (Pelgrom mismatch model), related through a technology constant. Also the influence of metal coverage on the mismatch of MOS transistors has been reported. In this work these results are verified. A test chip has been processed and measured. It is an actual implementation of a D/A-converter. From the static linearity measurements the mismatch behavior is extracted, including metal coverage and edge effects. The resulting mismatch error behaviour is important information for the design of future high accuracy circuits. This work paved the ground for the design of the first intrinsic 14 bit accuracy D/A-converter in CMOS known to the authors. I. INTRODUCTION The recent boom in telecommunications systems is pushing circuits to both higher frequencies and accuracy. Frequencies well above a few 1MHz and accuracies of 1 and 12 bit are very common nowadays. To combine both analog and digital in integrated circuits, CMOS is the technology of choice. It is to be expected that in the future, even more accurate circuits will thus be made in deep submicron CMOS technologies. At this time 1 and 12 bit CMOS D/A converters have been published [1], [2]. 14 bit intrinsic accuracy CMOS D/A converters have only recently been published [3], [4]. In this work the problems encountered during the design of a 14 bit intrinsic accuracy D/A converter in a standard : CMOS technology are discussed. In section II the segmented D/A converter architecture is explained. The current source array is discussed in detail in section III. The guidelines for matching devices are revised in section IV. Finally conclusions are formulated in section V. II. SEGMENTED CURRENT STEERING D/A CONVERTER In figure 1 the operation principle of a segmented current steering D/A converter is explained with a 12 bit example. The least significant bits (b! b3) of the digital code directly research associate of the National Fund of Scientific Research Fig. 1. Operation principle of a segmented D/A converter. steer switches which control binary weighted current sources (I LSB! 8I LSB ). The most significant bits (b4! b11) are thermometer decoded in a thermocoder and steer the switches of the unary current cells (I MSB ). The value that is applied with the most significant bits is translated into an equal amount of switches that is turned on. This is equivalent to a thermometer decoding of the applied value. The amount of bits implemented with binary weighted or equal current sources is the degree of segmentation. The higher the number of bits implemented with the unary current sources, the higher the degree of segmentation is. In an actual implementation the decoder is mostly implemented as a row/column decoder [], or sometimes as a synthesized decoder [3]. The complexity of the decoder quickly increases (and its speed decreases), when more bits are thermometer decoded. That s why often the unary array is split in more parts. In the case of a 14 bit converter, the four MSB are implemented with a first unary array, the next with the next unary array (with 32 times smaller current sources) and the LSBs with a binary weighted array. The decoder s outputs don t directly steer the switches. Instead an extra synchronization is inserted between the decoder and the switches in the form of a clocked latch. This is done to ensure that high-quality signals are applied to the switch transistors, since these determine the amount of glitch at the output. In the remainder of the paper these blocks will not further be discussed. The static accuracy of the D/A converter is characterized by ISBN: c STW, :79

2 3 G. Van der Plas et al. the Integral and Differential Non linearity (INL/DNL). These specifications quantify the deviation of the implemented converter s linearity from the ideal converter characterisitic. The INL and DNL are defined as follows: DNL[i] D level ic1, level i (1) INL[i] D level i, ideal i (2) The extreme values of INL and DNL are used to characterize the D/A converter. An INL of less than :LSB is required to have a D/A converter of full accuracy (that is the number of bits applied at the input is converted accurately). This also guarantees that the DNL is below 1LSB. The static accuracy of the converter is predominantly determined by the current source array. It is this building block which will now be discussed in more detail. III. CURRENT SOURCE ARRAY Depending on the segmentation chosen, the implementation of the current source array consists of implementing a number of binary weighted and parallel unary current sources. In this paper we assume that trimming or calibration is not acceptable (because of area overhead, increase in complexity, power consumption, ::: ). This means that the current sources should intrinsically achieve the accuracy required. The following effects are well-known to cause identical MOS transistors to sink unmatched currents: random mismatch distance effect voltage drops in biasing wires, power supply wires, ::: finite output impedance technology process gradients edge effects metal coverage temperature gradients In this list a number of categories can be considered. First there are the pure random effects (mismatch). Secondly there are random effects (process gradients) of which the size is not exactly known, but their profile shape does give extra information. Thirdly there are systematic effects of which the exact size is not known (edge effects, metal coverage), or is known (voltage drops, finite output impedance, temperature gradients). Facing these degenerative effects the accuracy of the current sources needs to be determined. Assume that all these effects contribute to the important static specifications of the D/Aconverter: Yield [%] σ(i)/i [%] Fig. 2. Yield of a 14 bit D/A converter as a function of current source mismatch. A. Mismatch Starting from the segmentation, Monte Carlo experiments are run to determine the yield given the random mismatch (area) of the devices [6]. In figure 2 the resulting plot is shown for the case of a 14 bit converter (with an INL < :LSB). Using the model of [7], and the biasing of the current source transistor the W and L of this NMOS transistor can be determined: 2 2.I / I 2 D A2 WL C 4A 2 V th WL.V GS,V th / 2 V GS, V th 1Volt I tot D 2mA 9 >= >; ) WLSB D 1:1m L LSB D 14m () DNL D DNL mismatch C DNL gradients C DNL edge C DNL metal C ::: (3) INL D INL mismatch C INL gradients C INL edge C INL metal C ::: (4) That means that part of the DNL/INL specification is consumed by mismatch, another part by edge effects, :::.Sincea number of these effects is statistical, only an expected DNL/INL value can be given, with a variance. Fig. 3. Current Source Array of a 14 bit D/A converter. This determines the sizes of the LSB current source MOS transistor. Since accurate matching is only possible when using identical devices, the unit transistor is chosen as a compromise between the unary current source and the binary current sources. Consider the current source array shown in figure 3. It is the STW/SAFE99

3 MOS Transistor Mismatch for High Accuracy Applications 31 array of a segmented 14 bit D/A converter with the units implemented as NMOS transistors. The 8 MSBs are implemented unary, the 6 LSBs are implemented with binary weighted current sources. The unit current source transistor is four times the LSB transistor size. All the unary current sources can thus be built up out of 16 units, the binaries out of appropriate parallel and serial connections of the units. The output impedance of the sources is high enough to prevent degradation of the linearity, due to output voltage changes. In this case the unary current source was split up over 16 units. It seemed the most likely configuration capable of achieving 14 bit accuracy. For 12 bit accuracy a unary current source split up over 4 units was required in [2]. Fig.. Microphotograph of the 14 bit D/A Converter. metal3 BINARY CURRENT SOURCES BINARY CURRENT SOURCES 64 rows On the chip photo in figure, the decoder can be seen at the top of the chip. In the middle the switch and latch array is situated. A clock driver completes the chip, to make it a fully functional D/A converter columns Fig. 4. Floorplan of the Current Source Array of a 14 bit D/A converter. B. Floorplan of the Current Source Array The current source array is implemented as one large, uniform array of units. The floorplan of the array is shown in figure 4. Its size is 68 columns by 64 rows. The unary current source units are spread across the array, symmetrically around the center. The reasoning behind this is that the spatial gradients, those that are known as well as those that are unknown, will be either cancelled or suppressed [3], [8]. The 16 units are connected as indicated on the figure. The switching scheme (the sequence in which the unary sources are turned on when the input code increases) used is the one presented in [8]. When these current sources are measured (further down in the paper), the current measured is the sum of all the units. The power and biasing is provided with horizontal metal1 lines. The units are flipped every next row to share the power and biasing lines between two rows. The units forming one unary current source are connected with lines vertically and with metal3 lines horizontally. The matrix of unary units is completely covered with metal1, and metal3. The binaries are also spread across four columns at the positions indicated: two columns in the middle of the left half of the matrix, two columns in the middle of the right half. The binaries are connected through and metal3 lines. Only in this case less lines are required. This results in less coverage of the binary current sources by lines. This can clearly be seen on figure : the lower density of lines is visually observable. DAC DNL [LSB] DAC Input Code x 1 4 Fig. 6. DNL Measurement of the D/A converter. C. Measurements In figure 6, a differential non-linearity (DNL) measurement is shown of the 14 bit D/A converter. From this plot the errors of individual unary current sources can be extracted, and associated with their location on the silicon. So using the measurement results shown in figure 6 and the switching scheme of [8], the individual errors of the unary current sources are extracted. It must be noted that the current errors relate to the sum of 16 individual units spread across the matrix as indicated on figure 4. The extracted profile is shown in figures 7 and 8. The virtual location of the sources on these figures is the location of the top left quadrant shown in grey on figure 4. As can be clearly seen on the error profiles, the errors are not at all caused by purely random mismatch. There is a strong correlation between position and error. In fact the noise seen on the plots is more related to measurement noise than to actual IEEE/ProRISC99

4 32 G. Van der Plas et al Averaged Error [LSB] Horizontal Position (a).8.6 Fig. 7. The errors of the unary current sources in the matrix Fig. 8. The errors of the unary current sources in the matrix, opposite angle. mismatch. The data is now analyzed as in [9]. Therefore we average the errors of the current sources in both the horizontal and vertical direction. The edges are left out. This is a process of trial and error. The resulting error profiles are shown in figures 9(a) and (b). Consider now figure 9(a). It shows the average error of the current source in column 1 uptill column 16. In reality this is the sum of the current units in columns 1, 34, 3 and 68 which is plotted on coordinate 1. It can clearly be seen that the first three columns of the matrix suffer from what is known as the edge effect. Since beyond columns 1 and 68 no dummy sources are laid out, the etching of the devices deviates from the etching inside the array. This effect is felt up till column three. Expressed as a distance this is about 1m. As predicted in [9], the current in the sources at the edges is lower than the current in the bulk of the matrix, for NMOS transistors. On the right side of the plot also a drop in current is noticeable. The current plotted there is the one generated by the neighbours of the binary current sources. This is explained by the fact that the metal coverage of the binaries is different (less wires), as predicted in [1]. The matching of identical MOS transistors is adversely 2 1 Averaged Error [LSB] Vertical Position (b) Fig. 9. Horizontal (a) and vertical (b) error profiles. affected by metal coverage. The vertical dimension of the current source matrix is smaller. This is because the unit is flat (and the matrix is 64 by 68 units). Therefore the error profile is less pronounced, see figure 9(b). One very strange effect is however noticeable. The edge effect is now only visible on one side. This can be explained by the fact that on the center of the rows no binary devices have been inserted. There is only one edge. What however remains unexplained is the fact that a drop is noticed at the edge, followed by an increase in the average current for row two. This is not predicted by [9] and no obvious explanation could be found. The distances are also much lower for the row edge effect, although also the third row could be considered to have edge effect related errors. This distance amounts to about m, compared to the 1m of the columns. IV. REVISED GUIDELINES In table I the rules proposed by [11] are summarized. These rules of course apply for high-accuracy applications, as have been investigated in this paper. A few additional remarks can be formulated: 1. Same surroundings has often been interpreted as being equivalent to adding edges of dummy devices around a matrix. This is sometimes not sufficient. In fact it depends on the requested accuracy, technology and probably orientation of the devices to determine how far the edges are felt and thus how many rows and columns of dummy cells are required. In our case the results indicate that three dummy rows/columns would be needed. 2. Same metal coverage has recently been reported as being im- STW/SAFE99

5 MOS Transistor Mismatch for High Accuracy Applications 33 TABLE I RULES FOR OPTIMUM MATCHING 1. Same structure 2. Same temperature 3. Same shape, same size 4. Minimum distance. Common-centroid geometries 6. Same orientation 7. Same surroundings 8. Non minimum size portant for matching in [1]. In this design the absence of metal 2 wires on neighbours is being felt. So the same surroundings should be complemented with same metal coverage. 3. The use of common-centroid geometries can be extended with the following remark. There is an optimum splitting for matching equal sources. If the sources are split in too few units, the systematic effects will cause large mismatches. By splitting in more units, all these (spatial) systematic effects are averaged out. Of course splitting in too much units does not bring any additional improvement, while the cost (extra wiring and parasitic resistance/capacitance) goes up. [8] A. Van Den Bosch, M. Borremans, J. Vandenbussche, G. Van der Plas, A. Marques, J. Bastos, G. Gielen, M. Steyaert, and W. Sansen, A 12 bit 2MHz Low Glitch CMOS D/A Converter, 1998, pp. pp [9] A. Pavasovic, A. G. Andreou, and C. R. Westgate, Characterization of subthreshold MOS mismatch in transistors for VLSI systems, Journal of VLSI Processing,, no. 1, pp. 7 8,Octobre [1] H. P. Tuinhout and M. Vertregt, Test Structures for Investigation of Metal Coverage Effects on Mosfet Matching, 1997, pp. pp , Vol. 1. [11] E. A. Vittoz, The Design of High-Performance Analog Circuits on Digital CMOS Chips, JSSC, vol. SC-2, no. 3, pp , March 198. V. CONCLUSIONS In this poster the matching behaviour of MOS transistors for high-accuracy applications was discussed. Based upon the actual implementation of a 14 bit current steering D/A converter the behaviour was analyzed. The existing knowledge on the topic was confirmed or disputed. The guidelines commonly used for the creation of optimally matching devices were reviewed and updated. VI. ACKNOWLEDGMENTS The authors wish to acknowledge S. Habinc of ESA-Estec. REFERENCES [1] C.-H. Lin and K. Bult, A 1b MSamples/s CMOS DAC in :6mm 2, JSSC, vol. SC-33, no. 12, pp , [2] A. Marques, J. Bastos, A. Van Den Bosch, J. Vandenbussche, M. Steyaert, and W. Sansen, A 12-bit Accuracy 3 MSample/s Update Rate CMOS DAC, in ISSCC Digest of technical papers, february 1998, pp , Slide suppl. pp. [3] J. Vandenbussche,G. Van der Plas, A. Van Den Bosch, W. Daems, G. Gielen, M. Steyaert, and W. Sansen, A 14-bit, MSamples/s Update Rate, Q 2 Random Walk CMOS DAC, 1999, pp. Digest of technical papers pp , Slide suppl. pp. [4] A. R. Bugeja, B.-S. Song, P.L. Rakers, and S. F. Gillig, A 14b 1MSamsple/s CMOS DAC Designed for Spectral Performance, 1999, pp. Digest of technical papers pp [] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, An 8-MHz 8-bit CMOS D/A Converter, JSSC, vol. SC-21, no. 6, pp , June [6] J. Bastos, M. Steyaert, and W. Sansen, A High Yield 12 bit 2MS/s CMOS D/A Converter, 1996, pp. pp [7] M. Pelgrom, A. Duinmaijer, and A. Welbers, Matching properties of MOS transistors, JSSC, vol. SC-24, no., pp , IEEE/ProRISC99

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