EE247 Lecture 14. EE247 Lecture 14

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1 EE47 Lecture 14 Administrative issues Midterm exam postponed to Thurs. Nov. 5th o You can only bring one 8x11 paper with your own written notes (please do not photocopy) o No books, class or any other kind of handouts/notes, calculators, computers, PDA, cell phones... o Midterm includes material covered to end of lecture 14 EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 1 EE47 Lecture 14 D/A converters D/A converters: Various Architectures (continued) Charge scaling DACs (continued) R-R type DACs Current based DACs Static performance of D/As Component matching Systematic & random errors Practical aspects of current-switched DACs Segmented current-switched DACs DAC dynamic non-idealities DAC design considerations EECS 47 Lecture 14: Data Converters- DAC Design 9 Page

2 Summary of Last Lecture Data Converters Data converter testing (continued) Dynamic tests (continued) Relationship between: DNL & SNR, INL & SFDR Effective number of bits (ENOB) D/A converters: Various Architectures Resistor string DACs Serial charge redistribution DACs Charge scaling DACs R-R type DACs Current based DACs EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 3 Charge Scaling DAC Utilizing Split Array reset 8/7C C C C 4C C C 4C + - Vout b b 1 b b 3 b 4 b 5 C series = all LSB array C C all MSB arrayc Vref Split array reduce the total area of the capacitors required for high resolution DACs E.g. 1bit regular binary array requires 14 unit Cs while split array (5&5) needs 64 unit Cs Issue: Sensitive to parasitic capacitor EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 4

3 Charge Scaling DAC Advantages: Low power dissipation capacitor array does not dissipate DC power Output is sample and held no need for additional S/H INL function of capacitor ratio Possible to trim or calibrate for improved INL Offset cancellation almost for free Disadvantages: Process needs to include good capacitive material not compatible with standard digital process Requires large capacitor ratios Not inherently monotonic (more later) EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 5 Segmented DAC Resistor Ladder (MSB) & Binary Weighted Charge Scaling (LSB) Example: 1bit DAC 6-bit MSB DAC R- string 6-bit LSB DAC binary weighted charge scaling reset 3 C 16C 8C 4C C C V out C Component count much lower compared to full R-. b 5 b 4 b 3 b b 1 b string Full R string 496 resistors Segmented 64 R + 7 Cs (64 unit caps) 6bit resistor ladder Switch Network 6-bit binary weighted charge redistribution DAC EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 6

4 Current Based DACs R-R Ladder Type R-R DAC basics: Simple R network divides both voltage & current by V R I V/ I/ I/ R R Increase # of bits by replicating circuit EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 7 R-R Ladder DAC I out V B V EE R R R R R R R R R R Emitter-follower added to convert to high output impedance current sources EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 8

5 R-R Ladder DAC How Does it Work? Consider a simple 3bit R-R DAC: I out V B 4xA unit xa unit 1xA unit 1xA unit V EE R R R R R R EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 9 Simple 3bit DAC: 1- Consolidate first two stages: R-R Ladder DAC How Does it Work? I 3 I I 1 I T I 3 I I 1 +I T V B Q 3 Q Q 1 Q T V B Q 3 Q 4A unit A unit A unit A unit 4A unit A unit A unit V EE R R R R R R V EE R R R R R EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 1

6 Simple 3bit DAC- - Consolidate next two stages: R-R Ladder DAC How Does it Work? I 3 I I 1 +I T I3 I +I 1 +I T V B Q 3 Q V B Q 3 Q 4A unit A unit A unit 4A unit 4A unit V EE R R R R R V EE R R I Total I Total I I Total 3 = I + I 1 + I I T 3 =,I =,I 4 1 = 8 R EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 11 Consider a simple 3bit R-R DAC: R-R Ladder DAC How Does it Work? I out V B 4A unit A unit A unit A unit V EE 4I R I R I R I R R R 4I I In most cases need to convert output current to voltage Ref: B. Razavi, Data Conversion System Design, IEEE Press, 1995, page EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 1

7 R-R Ladder DAC R Total - R + V out V B V EE 16I R 8I R 4I R I R I R I R R R R R 16I 8I 4I Trans-resistance amplifier added to: - Convert current to voltage - Generate virtual current summing node so that output impedance of current sources do not cause error - Issue: error due to opamp offset EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 13 I R-R Ladder DAC Opamp Offset Issue out in R Vos = V os 1 + RTotal If RTotal = large, out in Vos Vos If RTotal = not large out in R Vos Vos 1 = + RTotal Problem: R Total - V os + Offset Model R V out Since R Total is code dependant out V os would be code dependant Gives rise to INL & DNL EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 14

8 R-R Ladder Summary Advantages: Resistor ratios only x Does not require precision capacitors Disadvantages: Total device emitter area A E unitx B Not practical for high resolution DACs INL/DNL error due to amplifier offset EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 15 Current based DAC Unit Element Current Source DAC I out Unit elements or thermometer B -1 current sources & switches Suited for both MOS and BJT technologies Monotonicity does not depend on element matching and is guaranteed Output resistance of current source gain error Cascode type current sources higher output resistance less gain error EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 16

9 Current Source DAC Unit Element - R + Vout Output resistance of current source gain error problem Use transresistance amplifier - Current source output virtual ground - Error due to current source output resistance eliminated - New issues: offset & speed of the amplifier EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 17 Current Source DAC Binary Weighted I out B-1 4 Binary weighted B current sources & switches ( B -1 unit current sources but less # of switches) Monotonicity depends on element matching not guaranteed EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 18

10 Static DAC Errors -INL / DNL Static DAC errors mainly due to component mismatch Systematic errors Contact resistance Edge effects in capacitor arrays Process gradients Finite current source output resistance Random variations Lithography etc Often Gaussian distribution (central limit theorem) *Ref: C. Conroy et al, Statistical Design Techniques for D/A Converters, JSSC Aug. 1989, pp EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 19 Current Source DAC DNL/INL Due to Element Mismatch - + Vout -ΔI +ΔI Simplified example: 3-bit DAC Assume only two of the current sources mismatched (# 4 & #5) EECS 47 Lecture 14: Data Converters- DAC Design 9 Page

11 Current Source DAC DNL/INL Due to Element Mismatch segment[m] V[LSB] DNL[m] = V[LSB] segment[4] V[LSB] DNL[4] = V[LSB] (I ΔI)R IR = IR DNL[4] = ΔI / I [LSB] 7 R Analog Output (I+ΔI)R IR DNL[5] = IR DNL[5] =ΔI / I[LSB] INL max = ΔI / I [LSB] 1x R Digital Input EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 1 Component Mismatch Probability Distribution Function Component parameters Random variables Each component is the product of many fabrication steps Most fabrication steps includes random variations Overall component variations product of several random variables Assuming each of these variables have a uniform pdf distribution: Joint pdf of a random variable affected by two uniformly distributed variables convolution of the two uniform pdfs. pdf [f(x1,x)] * pdf [f(x1)] * pdf [f(x)] pdf [f(x3,x4)].... pdf [f(x1,x)] pdf [f(xm,xn)] * Gaussian pdf EECS 47 Lecture 14: Data Converters- DAC Design 9 Page

12 Gaussian Distribution Probability density p(x) ( x μ) 1 p( x ) = e σ πσ where: μ is the expected value and standard deviation : σ = E( X ) μ σ variance (x-μ) /σ EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 3 In most cases we are interested in finding the percentage of components (e.g. R) falling within certain bounds: P X x + X = ( ) = 1 π + X x e X dx Probability density p(x) X = erf Integral has no analytical solution found by numerical methods P(-X x +X) Yield X/σ EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 4

13 Yield X/σ P(-X x X) [%] X/σ P(-X x X) [%] EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 5 Example Measurements show that the offset voltage of a batch of operational amplifiers follows a Gaussian distribution with σ = mv and μ =. Find the fraction of opamps with V os < 6mV: X/σ = % yield Fraction of opamps with V os < 4μV: X/σ = % yield EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 6

14 Example: Resistors layouted out side-by-side. After fabrication large # of devices measured & graphed typically if sample size large shape is Gaussian Component Mismatch. No. of resistors ΔR R R[ Ω] E.g. Let us assume in this example 1 Rs measured & 68.5% fall within +-4OHM or +-.4% of average 1σ for resistors.4% EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 7 Example: Two resistors layouted out side-by-side R1+ R R = dr= R R dr R 1 1 σ Area Component Mismatch Probability density p(x) σ σ σ ΔR R For typical technologies & geometries 1σ for resistors. to 5% In the case of resistors σ is a function of area σ σ 3σ dr R EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 8

15 DNL Unit Element DAC E.g. Resistor string DAC: Assumption: No systematic error- only random error Δ= R I where R = Δ= RI i median ref median i ref B 1 i o B R V ref Δ Δ i DNLi = Δ median median Δ=RI i i ref σ DNL = = R R R Ri R median dr dr = σ dr R median i i median i To first order DNL of unit element DAC is independent of resolution! Note: Similar results for other unit-element based DACs EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 9 DNL Unit Element DAC E.g. Resistor string DAC: σ DNL = σ dr R i i Example: If σ dr/r =.4%, what DNL spec goes into the DAC datasheet so that 99.9% of all converters meet the spec? EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 3

16 Yield X/σ P(-X x X) [%] X/σ P(-X x X) [%] EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 31 DNL Unit Element DAC E.g. Resistor string DAC: σ DNL = σ dr R i i Example: If σ dr/r =.4%, what DNL spec goes into the datasheet so that 99.9% of all converters meet the spec? Answer: From table: for 99.9% X/σ = 3.3 σ DNL = σ dr/r =.4% 3.3 σ DNL = 3.3x.4%=1.3% DNL= +/-.13 LSB EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 3

17 DAC INL Analysis N Ideal Variance A=n+E n n.σ ε Output [LSB] n B E A n Input [LSB] N= B -1 B=N-n-E N-n (N-n).σ ε E = A-n r =n/n N=A+B = A-r(A+B) = (1-r). A - r.b Variance of E: σ E =(1-r).σ Α + r.σ B =N.r.(1-r).σ ε = n.(1- n/n).σ ε EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 33 DAC INL σ INL /σ ε n σe = n 1 σ ( ε B -1).5 / N dσ E To find max. variance: = dn N n= N / σe = σε 4 Error is maximum at mid-scale (N/): σ INL 1 B 1 = σε B with N = n/n INL depends on both DAC resolution & element matching σ ε While σ DNL = σ ε is to first order independent of DAC resolution and is only a function of element matching Ref: Kuboki et al, TCAS, 6/198 EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 34

18 Untrimmed DAC INL Example: Assume the following requirement for a DAC: σ INL =.1 LSB Find maximum resolution for: σε = 1% Bmax = 8.6bits σε =.5% Bmax = 1.6bits σε =.% Bmax = 13.3bits σ =.1% B = 15.3bits ε max 1 B 1 Note: In most cases, a number of systematic errors prevents achievement of above results σ INL B + log σ σ σ ε INL ε EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 35 DNL [LSB] 1 Simulation Example 1 Bit converter DNL and INL -.4 / +.3 LSB σ ε = 1% B = 1 Random # generator used in MatLab INL LSB] bin -. / +.8 LSB bin Computed INL: σ INL max =.3 LSB (midscale) Why is the results not as expected per our derivation? EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 36

19 INL & DNL for Binary Weighted DAC INL same as for unit element DAC I out DNL depends on transition Example: to 1 σ DNL = σ (dι/ι) 1 to σ DNL = 3σ (dι/ι) B-1 4 Consider MSB transition: EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 37 I 8 I 4 I I DAC DNL Example: 4bit DAC I out DNL depends on transition Example: to 1 σ DNL = σ (dιref/ιref) 1 to σ DNL = 3σ (dιref/ιref) Analog Output [ ] I on 4,I off,i off 1 I on,i on 1 I on,i 1 off. I on 8, I off 4,I off,i off 1 I 8 off, I 4 on,i on,i 1 on 1 I on 1 Digital Input EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 38.

20 Binary Weighted DAC DNL σ DNL / σ ε DNL for a 4-Bit DAC DAC Output [LSB] Worst-case transition occurs at mid-scale: ( 1) ε ( ) B 1 B 1 DNL = + ε σ σ σ Bσ ε σdnl = B/ max σε 1 B 1 σinlmax 1 σε σdnl max Example: B = 1, σ ε = 1% σ DNL =.64 LSB σ INL =.3 LSB EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 39 d d MOS Current Source Variations Due to Device Matching Effects Id1+ I Id = di I I = I I d d d1 d d W L W L did d dv = + I V V GS th th Current matching depends on: - Device W/L ratio matching Larger device area less mismatch effect - Current mismatch due to threshold voltage variations: Larger gate-overdrive less threshold voltage mismatch effect I d1 I d EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 4

21 Current-Switched DACs in CMOS I out Switch Array di W d d L dvth = + I V V W d L GS th Advantages: Example: 8bit Binary Weighted Can be very fast Reasonable area for resolution < 9-1bits Disadvantages: Accuracy depends on device W/L & V th matching EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 41 Unit Element versus Binary Weighted DAC Unit Element DAC σ = σ DNL ε B 1 σ σ INL ε Binary Weighted DAC B σ σ = σ DNL ε INL B 1 σ σ INL ε Number of switched elements: S = B S = B Key point: Significant difference in performance and complexity! EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 4

22 Unit Element versus Binary Weighted DAC Example: B=1 Unit Element DAC Binary Weighted DAC σ DNL = σ ε σ DNL = B σ 3 ε σ ε 1 σ σ 6σ B INL = 1 ε ε σ INL Number of switched elements: 1 = B σ 16 ε σ ε B S = = 14 S = B= 1 Significant difference in performance and complexity! EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 43 Another Random Run DNL [LSB] INL [LSB] DNL and INL of 1 Bit converter -1 / +.1 LSB, bin -.8 / +.8 LSB bin Now (by chance) worst DNL is mid-scale. Close to statistical result! EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 44

23 1Bit DAC DNL/INL Comparison Plots: 1 Simulation Runs Overlaid Ref: C. Lin and K. Bult, "A 1-b, 5- MSample/s CMOS DAC in.6 mm," IEEE Journal of Solid-State Circuits, vol. 33, pp , December Note: σ ε =% EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 45 1Bit DAC DNL/INL Comparison Plots: RMS for 1 Simulation Runs Ref: C. Lin and K. Bult, "A 1-b, 5- MSample/s CMOS DAC in.6 mm," IEEE Journal of Solid-State Circuits, vol. 33, pp , December Note: σ ε =% EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 46

24 DAC INL/DNL Summary DAC choice of architecture has significant impact on DNL INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision Results assume uncorrelated random element variations Systematic errors and correlations are usually also important and may affect final DAC performance Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D converters. IEEE Transactions on Circuits and Systems, vol.cas-9, (no.6), June 198. p EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 47 Segmented DAC Combination of Unit-Element & Binary-Weighted Objective: Compromise between unit-element and binary-weighted DAC MSB (B1 bits) (B bits) LSB Unit Element Binary Weighted Approach: B 1 MSB bits unit elements B LSB bits binary weighted V Analog B Total = B 1 +B INL: unaffected same as either architecture DNL: Worst case occurs when LSB DAC turns off and one more MSB DAC element turns on Same as binary weighted DAC with (B +1) # of bits Number of switched elements: ( B1-1) + B EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 48

25 Comparison Example: B = 1, B 1 = 5, B = 7 B 1 = 6, B = 6 MSB Assuming: σ ε = 1% DAC Architecture (B1+B) Unit element (1+) Segmented (6+6) Segmented (5+7) Binary weighted(+1) LSB σ INL[LSB] DNL INL ( B + 1) σ σ = σ σ B B1 1 σ ε ε S = 1+ B σ DNL[LSB] INL # of switched elements = =38 1 EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 49 Practical Aspects Current-Switched DACs Unit element DACs ensure monotonicity by turning on equal-weighted current sources in succession Typically current switching performed by differential pairs For each diff pair, only one of the devices are on switch device mismatch not an issue Issue: While binary weighted DAC can use the incoming binary digital word directly, unit element requires a decoder Binary Thermometer 1 1 N to ( N -1) decoder EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 5

26 4-bit MSB Unit element DAC + 4-bit binary weighted DAC Note: 4-bit MSB DAC requires extra 4-to-16 bit decoder Digital code for both DACs stored in a register Segmented Current-Switched DAC Example: 8bit 4MSB+4LSB EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 51 Segmented Current-Switched DAC Cont d 4-bit MSB Unit element DAC + 4- bit binary weighted DAC Note: 4-bit MSB DAC requires extra 4-to-16 bit decoder Digital code for both DACs stored in a register EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 5

27 Segmented Current-Switched DAC Cont d MSB Decoder Domino logic Example: D4,5,6,7=1 OUT=1 Domino Logic Register Latched NAND gate: CTRL=1 OUT=INB IN Register EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 53 Segmented Current-Switched DAC Reference Current Considerations is referenced to V DD Problem: Reference current varies with supply voltage + - =(V DD -V ref ) / R EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 54

28 is referenced to V ss GND Segmented Current-Switched DAC Reference Current Considerations + - =(V ref -V ss ) / R EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 55 Segmented Current-Switched DAC Considerations Example: bit MSB Unit element DAC & 3bit binary weighted DAC To ensure monotonicity at the MSB LSB transition: First OFF MSB current source is routed to LSB current generator LSB MSB EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 56

29 DAC Dynamic Non-Idealities Finite settling time Linear settling issues: (e.g. RC time constants) Slew limited settling Spurious signal coupling Coupling of clock/control signals to the output via switches Timing error related glitches Control signal timing skew EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 57 Dynamic DAC Error: Timing Glitch Consider binary weighted DAC transition 11 1 DAC output depends on timing Plot shows situation where the control signals for LSB & MSB LSB/MSBs on time LSB early, MSB late LSB late, MSB early Ideal Late 1 5 Early DAC Output Time EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 58

30 Glitch Energy Glitch energy (worst case) proportional to: dt x B-1 dt error in timing & B-1 associated with half of the switches changing state LSB energy proportional to: T=1/f s Need dt x B-1 << T or dt << -B+1 T Examples: f s [MHz] 1 1 B dt [ps] << 488 << 1.5 <<.5 Timing accuracy for data converters much more critical compared to digital circuitry EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 59 DAC Dynamic Errors To suppress effect of non-idealities: Retiming of current source control signals Each current source has its own clocked latch incorporated in the current cell Minimization of latch clock skew by careful layout ensuring simultaneous change of bits To minimize control and clock feed through to the output via G-D & G-S of the switches Use of low-swing digital circuitry EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 6

31 DAC Implementation Examples Untrimmed segmented T. Miki et al, An 8-MHz 8-bit CMOS D/A Converter, JSSC December 1986, pp. 983 A. Van den Bosch et al, A 1-GSample/s Nyquist Current-Steering CMOS D/A Converter, JSSC March 1, pp. 315 Current copiers: D. W. J. Groeneveld et al, A Self-Calibration Technique for Monolithic High-Resolution D/A Converters, JSSC December 1989, pp Dynamic element matching: R. J. van de Plassche, Dynamic Element Matching for High- Accuracy Monolithic D/A Converters, JSSC December 1976, pp. 795 EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 61 8x8 array μ tech., 5Vsupply 6+ segmented EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 6

32 Two sources of systematic error: - Finite current source output resistance - Voltage drop due to finite ground bus resistance EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 63 Current-Switched DACs in CMOS Assumptions: RxI small compared to transistor gate-overdrive To simplify analysis: Initially, all device currents assumed to be equal to I V = V 4RI GS M GS M1 V = V 7RI GS M3 GS M1 I out V = V 9RI GS GS M4 M5 = I1 GS GS M1 V = V 1RI I I = k M1 ( VGS Vth) M 1 V GS 4RI M1 V th V G V DD M 5 M 1 I M 1 I M 3 M I 4 3 I 4 I 5 Rx4I Rx3I RxI RxI Example: 5 unit element current sources EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 64

33 Current-Switched DACs in CMOS 4RI I = k( VGS V ) M th = I 1 1 VGS V M1 th I g 1 m = M1 VGS V M1 th 4Rgm M1 I I1 1 I1 1 4Rgm = ( ) 7Rgm m ( ) M1 I I I 1 7Rg = 9Rgm m ( ) M1 I I I 1 9Rg = 1Rgm m ( ) M1 I I I 1 1Rg = Desirable to have g m small M1 M1 M1 M1 I out V DD M 5 M 1 I M 1 I M 3 I M 4 3 I 4 I 5 Rx4I Rx3I RxI RxI Example: 5 unit element current sources EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 65 INL [LSB] Current-Switched DACs in CMOS Example: INL of 3-Bit unit element DAC Input Sequential current source switching Symmetrical current source switching Example: 7 unit element current source DAC- assume g m R=1/1 If switching of current sources arranged sequentially ( ) INL= +.5LSB If switching of current sources symmetrical ( ) INL = +.9, -.58LSB INL reduced by a factor of.6 EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 66

34 Current-Switched DACs in CMOS Example: DNL of 7 unit element DAC. DNL [LSB] Sequential current source switching Symmetrical current source switching Input Example: 7 unit element current source DAC- assume g m R=1/1 If switching of current sources arranged sequentially ( ) DNL max = +.15LSB If switching of current sources symmetrical ( ) DNL max = +.15LSB DNL max unchanged EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 67 Two sources of systematic error: - Finite current source output resistance - Voltage drop due to finite ground bus resistance EECS 47 Lecture 14: Data Converters- DAC Design 9 Page 68