Summary of Last Lecture

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1 EE247 Lecture 2 ADC Converters (continued) Successive approximation ADCs (continued) Flash ADC Flash ADC sources of error Sparkle code Meta-stability Comparator design EECS 247 Lecture 2: Data Converters 26 H.K. Page Summary of Last Lecture ADC Converters Sampling (continued) Track & hold circuits T/H combined with summing/difference function T/H circuit incorporating gain & offset cancellation Electro-Static Discharge (ESD) protection ADC architectures Serial- slope type Successive approximation EECS 247 Lecture 2: Data Converters 26 H.K. Page 2

2 Successive Approximation ADC Example: 6-bit ADC & V IN =5/8V REF V IN T/H V REF Control Logic DAC V DAC /V REF ADC /2 3/4 5/8 /6 2/32 4/64 3/4 5/8 /2 V IN Clock Test MSB Test MSB- Time / Clock Ticks High accuracy achievable (6+ Bits) Require N clock cycles for N-bit conversion (much faster than slope type) Moderate speed proportional to B (MHz range) EECS 247 Lecture 2: Data Converters 26 H.K. Page 3 Example: SAR ADC Charge Redistribution Type S top Comparator 32C 6C 8C 4C 2C C C - Out b 4 (msb) b 3 b 3 b 2 b b V in Control Logic To switches V REF V in T/H inherent in DAC Operation starts by connecting all top plate to gnd and all bottom plates to Vin To test the MSB all top plate are opened bottom plate of 32C connected to V REF & rest of bottom plates connected to ground input to comparator= -V in +V REF /2 Comparator is strobed to determine the polarity of input signal if - MSB= if + MSB= The process continues until all bits are determined EECS 247 Lecture 2: Data Converters 26 H.K. Page 4

3 Example: SAR ADC Charge Redistribution Type reset C P -Comparator 32C 6C 8C 4C 2C C C Out b 4 (msb) b 3 b 3 b 2 b b V in Control Logic To switches V REF V in To st order parasitic (C p ) insensitive since top plate driven from initial to final by the global negative feedback Linearity is a function of accuracy of C ratios Possible to add a C ratio calibration cycle (see ref.) Ref: H. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 5 bit CMOS A/D converter," IEEE Journal of Solid-State Circuits, vol. 9, pp , December 984. EECS 247 Lecture 2: Data Converters 26 H.K. Page 5 B-bit flash ADC: DAC generates all possible 2 B - levels 2 B - comparators compare V IN to DAC outputs Flash ADC V REF V IN f s Comparator output: If V DAC < V IN If V DAC > V IN D A C 2 B - B Encoder Digital Output Comparator outputs form thermometer code Encoder converts thermometer to binary code EECS 247 Lecture 2: Data Converters 26 H.K. Page 6

4 Flash ADC Converter Example: 3-bit Conversion V IN V IN V REF V REF f s Thermometer code Encoder B-bits Time EECS 247 Lecture 2: Data Converters 26 H.K. Page 7 Flash Converter Very fast: only clock cycle per conversion Half cycle V IN & V DAC comparison Half cycle 2 B - to B encoding High complexity: 2 B - comparators V IN V REF f s Encoder Input capacitance of 2 B - comparators connected to the input node: High input node Thermometer code B-bits EECS 247 Lecture 2: Data Converters 26 H.K. Page 8

5 Flash Converter Sources of Error V REF V IN f s R/2 R R R R R/2. Encoder Digital Output Comparator input: Offset Nonlinear input capacitance Kickback noise (disturbs reference) Signal dependent sampling time Comparator output: Sparkle codes ( ) Metastability EECS 247 Lecture 2: Data Converters 26 H.K. Page 9 Flash Converter Example: 8-bits ADC 8-bits 255 comparators R/2 V REF V IN f s V REF =V LSB=4mV R R DNL</2LSB Comparator input referred offset < 2mV R. Encoder Digital Output R 2mV =6σ offset σ offset <.33mV R/2 EECS 247 Lecture 2: Data Converters 26 H.K. Page

6 Flash ADC Converter Example: 8-bits ADC (continued) σ Offset <.33mV Let us assume in the technology used: Voffset-per-unit-sqrt(WxL)=3 [mvx μ] 3[ mv μ] 2 V ffset = =.33mV W L= 83μ W L 2 2 Assuming: Cox = 9 ff/ μ CGS = CoxW L= 496 ff 3 Total input capacitance: = 26.5 pf! Issues: Si area quite large Large input capacitance Since depending on input voltage different number of comparator input transistors would be on/off- total input capacitance varies as input varies Nonlinear input capacitance could give rise to signal distortion particularly at high frequencies Ref: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp , October 989. EECS 247 Lecture 2: Data Converters 26 H.K. Page Flash ADC Converter Example (continued) Trade-offs: Allowing larger DNL e.g. LSB instead of.5lsb: Increases the maximum allowable input-referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduces the input capacitance by a factor of 4! Reducing the ADC resolution by -bit Increases the maximum allowable input-referred offset voltage by a factor of 2 Decreases the required device WxL by a factor of 4 Reduces the input device area by a factor of 4 Reduce the input capacitance by a factor of 4 Add offset cancellation to the comparator and thus decrease the input device area could reduce the conversion rate EECS 247 Lecture 2: Data Converters 26 H.K. Page 2

7 Flash Converter Maximum Tolerable Comparator Offset versus ADC Resolution Assumption: DNL=.5LSB Note: Graph shows offset, note that depending on min acceptable yield, the derived offset numbers are associated with 2σ to 6σ offset voltage Maximum Comparator V offset [mv] 2 - V REF =2V V REF =V ADC Resolution EECS 247 Lecture 2: Data Converters 26 H.K. Page 3 Typical Flash Output Encoder Binary Output (negative) V DD b3 b2 bb Thermometer to Binary encoder ROM Thermometer code -of-n decoding Final encoding NOR ROM Ideally, for each code, only one ROM row is activated b3 b2 b b Output EECS 247 Lecture 2: Data Converters 26 H.K. Page 4

8 Sparkle Codes V DD Erroneous (comparator offset?) b3 b2 bb Correct Output: Problem: Two rows are on Erroneous Output: /2FS error! EECS 247 Lecture 2: Data Converters 26 H.K. Page 5 Sparkle Tolerant Encoder Protects against a single sparkle. Ref: C. Mangelsdorf et al, A 4-MHz Flash Converter with Error Correction, JSSC February 99, pp EECS 247 Lecture 2: Data Converters 26 H.K. Page 6

9 Meta-Stability X Different gates interpret metastable output X differently Correct output: Erroneous output: Solutions: Extra latches following comparator (high power) Gray encoding Ref: C. Portmann and T. Meng, Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters, JSSC August 996, pp EECS 247 Lecture 2: Data Converters 26 H.K. Page 7 Gray Encoding Thermometer Code Gray Binary T 7 T 6 T 5 T 4 T 3 T 2 T G 3 G 2 G B 3 B 2 B G = T T + T T G G = T T = T Each T i affects only one G i Avoids disagreement of interpretation by multiple gates Protects also against sparkles Follow Gray encoder by (latch and) binary encoder EECS 247 Lecture 2: Data Converters 26 H.K. Page 8

10 Voltage Comparators V DD V i+ V i V out (Digital Output) Play an important role in majority of ADCs Function: Compare the instantaneous value of two analog signals & generate a digital output voltage based on the sign of the difference: If V i+ -V i- > V out = If V i+ -V i- < V out = EECS 247 Lecture 2: Data Converters 26 H.K. Page 9 Voltage Comparator Architectures Comparator architectures High gain amplifier with differential analog input & single-ended large swing output Output swing compatible with driving digital logic circuits Open-loop amplification no frequency compensation required Precise gain not required Latched comparators; in response to a strobe, input stage disabled & digital output stored in a latch till next strobe Two options for implementation : Latch-only comparator Low-gain amplifier + high-sensitivity latch Sample-data comparators T/H input Offset cancellation EECS 247 Lecture 2: Data Converters 26 H.K. Page 2

11 Comparators w/ High-Gain Amplification Amplify V in (min) to V DD V in (min) determined by ADC resolution Example: 2-bit ADC with: -V FS =.5V LSB=.36mV -V DD =.8V For.8V output &.5LSB precision: Min.8V Av =,.8mV EECS 247 Lecture 2: Data Converters 26 H.K. Page 2 f u u Comparators -Single-Stage Amplification = unity-gain frequency, f =-3dB frequency fu f= o AV Example: f =GHz & A =, GHz fo = khz, τsettling = =.6μsec 2π fo Allowa few τ for output to settle Max. fclock 26kHz 5τ settling V o A v Gain f u =.-GHz f f u frequency Assumption: Single pole amplifier Too slow! Try cascade of lower gain stages to broadband response EECS 247 Lecture 2: Data Converters 26 H.K. Page 22

12 Comparators 2- Cascade of Open Loop Amplifiers The stages identical small-signal model for the cascades: One stage: EECS 247 Lecture 2: Data Converters 26 H.K. Page 23 Open Loop Cascade of Amplifiers EECS 247 Lecture 2: Data Converters 26 H.K. Page 24

Open Loop Cascade of Amplifiers For A T (DC) =, Example: N=3, f =GHz & A () = u GHz /3 fon = 2 23.

Clock o A llowa few τ for output to settle f 29MHz 5τ settling T f max improved from 26kHz to 29MHz x225 EECS 247 Lecture 2:

13 Open Loop Cascade of Amplifiers For A T (DC) =, Example: N=3, f =GHz & A () = u GHz /3 fon = MHz /3 (,) τ settling = = 7nsec 2π f Max. Clock o A llowa few τ for output to settle f 29MHz 5τ settling T f max improved from 26kHz to 29MHz x225 EECS 247 Lecture 2: Data Converters 26 H.K. Page 25 Open Loop Cascade of Amplifiers Offset Voltage From offset point of view high gain/stage is preferred Choice of # of stage bandwidth vs offset tradeoff EECS 247 Lecture 2: Data Converters 26 H.K. Page 26

14 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior t EECS 247 Lecture 2: Data Converters 26 H.K. Page 27 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior EECS 247 Lecture 2: Data Converters 26 H.K. Page 28

Open Loop Cascade of Amplifiers Delay/(C/g m ) Minimum total delay broad function of N Relationship between # of stages that minimize delay (N op ) and gain (V out /V in )

23, pp. 379-385, December 988. EECS 247 Lecture 2: Data Converters 26 H.K.

amp can be cancelled by storing it in series with either the input or the output of that stage Offset can be cancelled by adding a pair of auxiliary inputs to the amplifier

15 Open Loop Cascade of Amplifiers Delay/(C/g m ) Minimum total delay broad function of N Relationship between # of stages that minimize delay (N op ) and gain (V out /V in ) approximately: Delay/(C/g m ) N opt + log 2 A T for A< N opt.2lna T for A Ref: J.T. Wu, et al., A -MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp , December 988. EECS 247 Lecture 2: Data Converters 26 H.K. Page 29 Offset Cancellation In sampled-data cascade of amplifiers Vos can be cancelled Store on ac-coupling caps in series with amp stages Offset associated with a specific amp can be cancelled by storing it in series with either the input or the output of that stage Offset can be cancelled by adding a pair of auxiliary inputs to the amplifier and storing the offset on capacitors connected to the aux. inputs during offset cancellation phase Ref: J.T. Wu, et al., A -MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp , December 988. EECS 247 Lecture 2: Data Converters 26 H.K. Page 3

16 Offset Cancellation Output Series Cancellation Amp modeled as ideal + V os (input referred) Store offset: S, S4 open S2, S3 closed V C =AxV OS Ref: J.T. Wu, et al., A -MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp , December 988. EECS 247 Lecture 2: Data Converters 26 H.K. Page 3 Offset Cancellation Output Series Cancellation Amplify: S, S4 closed S2, S3 open V C =AxV OS Circuit requirements: Amp not saturate during offset storage High-impedance (C) load C c not discharged C c >> C L to avoid attenuation C c >> C switch offset due to charge injection EECS 247 Lecture 2: Data Converters 26 H.K. Page 32

17 Offset Cancellation Cascaded Output Series Cancellation EECS 247 Lecture 2: Data Converters 26 H.K. Page 33 Offset Cancellation Cascaded Output Series Cancellation - S open, S2,3,4,5 closed V C =A xv os V C2 =A 2 xv os2 V C3 =A xv os3 EECS 247 Lecture 2: Data Converters 26 H.K. Page 34

18 Offset Cancellation Cascaded Output Series Cancellation 2- S3 open Feedthrough from S3 offset on X Switch offset, ε 2 induced on node X Since S4 remains closed, offset associated with ε 2 stored on C2 V X = ε 2 V C =A xv os - ε 2 V C2 =A 2 x(v os2 + ε 2 ) EECS 247 Lecture 2: Data Converters 26 H.K. Page 35 Offset Cancellation Cascaded Output Series Cancellation 3- S4 open Feedthrough from S4 offset on Y Switch offset, ε 3 induces error on node Y Since S5 remains closed, offset associated with ε 3 stored on C3 V Y = ε 3 V C2 =A 2 x(v os2 + ε 2 ) - ε 3 V C3 =A 3 x(v os3 + ε 3 ) EECS 247 Lecture 2: Data Converters 26 H.K. Page 36

19 Offset Cancellation Cascaded Output Series Cancellation 4- S2 open, S closed, S5 open S closed & S2 open since input connected to low impedance source charge injection not of major concern Switch offset, ε 4 introduced due to S5 opening EECS 247 Lecture 2: Data Converters 26 H.K. Page 37 Offset Cancellation Cascaded Output Series Cancellation EECS 247 Lecture 2: Data Converters 26 H.K. Page 38

20 Offset Cancellation Cascaded Output Series Cancellation Example: 3-stage open-loop differential amplifier with offset cancellation + output amplifier (see ref.) A Total (DC) = 2x 6 = 2dB Input-referred offset < 5μV Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid- State Circuits, vol. 3, pp , August 978. EECS 247 Lecture 2: Data Converters 26 H.K. Page 39 Offset Cancellation Output Series Cancellation Advantages: Compete cancellation Closed-loop stability not required Disadvantages: Gain per stage must be small Offset storage C in the signal path- could slow down overall performance EECS 247 Lecture 2: Data Converters 26 H.K. Page 4

21 Offset Cancellation Input Series Cancellation Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid- State Circuits, vol. 3, pp , August 978. EECS 247 Lecture 2: Data Converters 26 H.K. Page 4 Store offset Offset Cancellation Input Series Cancellation Note: Mandates closed-loop stability Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid- State Circuits, vol. 3, pp , August 978. EECS 247 Lecture 2: Data Converters 26 H.K. Page 42

22 Offset Cancellation Input Series Cancellation Amplify S2, S3 open S closed EECS 247 Lecture 2: Data Converters 26 H.K. Page 43 Offset Cancellation Cascaded Input Series Cancellation ε 2 charge injection associated with opening of S4 EECS 247 Lecture 2: Data Converters 26 H.K. Page 44

23 Offset Cancellation Input Series Cancellation Advantages: In applications such as C-array successive approximation ADCs can use C-array to store offset Disadvantages: Cancellation not complete Requires closed loop stability Offset storage C in the signal path- could slow down overall performance EECS 247 Lecture 2: Data Converters 26 H.K. Page 45 CMOS Comparators Cascade of Gain Stages Fully differential gain stages st order cancellation of switch feedthrough offset -Output series offset cancellation 2- Input series offset cancellation EECS 247 Lecture 2: Data Converters 26 H.K. Page 46

24 CMOS Comparators Cascade of Gain Stages 3-Combined input & output series offset cancellation EECS 247 Lecture 2: Data Converters 26 H.K. Page 47 Offset Cancellation Cancel offset by additional pair of inputs (Lecture 2 slide 6 &7) EECS 247 Lecture 2: Data Converters 26 H.K. Page 48

25 Latched Comparators V i+ V i V out (Digital Output) V i+ - V i- Latch t Compares two input voltages at time t x & generates a digital output: Latch t x t If V i+ -V i- > V out = If V i+ -V i- < V out = V out t EECS 247 Lecture 2: Data Converters 26 H.K. Page 49 CMOS Latched Comparators Comparator amplification need not be linear can use a latch regeneration Latch Amplification + positive feedback EECS 247 Lecture 2: Data Converters 26 H.K. Page 5

26 CMOS Latched Comparators Small Signal Model Latch can be modeled as a: Single-pole amp + positive feedback Small signal ac half circuit EECS 247 Lecture 2: Data Converters 26 H.K. Page 5 CMOS Latched Comparator Latch Delay V dv gv m = + C RL dt gm dv gm dv V dt C gmr = L dt C gmr = L V g t2 V2 a m a a Integrating both sides: dt dv dx ln x b ln a ln b ln C g t V b mr = = = = L V x b Latch Delay: C V2 td = t2 t = ln g m V gmr L For g R >> m L C V 2 D ln g m V t EECS 247 Lecture 2: Data Converters 26 H.K. Page 52

CMOS Latched Comparators Normalized Latch Delay t D C V2 td ln g m V V2 Latch Gain = A V t D C ln A g m L L C g Compared to a 3-stage open-loop cascade of amps for equal overall gain of Latch faster

27 CMOS Latched Comparators Normalized Latch Delay t D C V2 td ln g m V V2 Latch Gain = A V t D C ln A g m L L C g Compared to a 3-stage open-loop cascade of amps for equal overall gain of Latch faster by about x3 m EECS 247 Lecture 2: Data Converters 26 H.K. Page 53 Latch-Only Comparator Main problem associated with latch-only comparator topology: High input-referred offset voltage (as high as mv!) Solution: Use preamplifier to amplify the signal and reduce overall input-referred offset EECS 247 Lecture 2: Data Converters 26 H.K. Page 54

28 V i+ Pre-Amplifier + Latch Overall Input-Referred Offset V Latch V Preamp os os D o+ A Latch V v i- D o- Preamp f s Latch offset attenuated by preamp gain when referred to preamp input Assuming the two offset sources are uncorrelated: σ σ σ 2 2 Input Re ferred _ Offset = Vos _ Pr eamp + 2 Vos _ Latch APr eamp Example : σ = 4 mv & σ = 5 mv & A = σ Vos _Pr eamp Vos _ Latch Preamp = = 6.4mV 2 2 Input Re ferred _ Offset 2 EECS 247 Lecture 2: Data Converters 26 H.K. Page 55 Pre-Amplifier Tradeoffs f s V i+ D o+ A Latch V v i- D o- Preamp Example: Latch offset 5 to mv Preamp DC gain X Preamp input-referred latch offset 5 to mv Input-referred preamplifier offset 2 to mv Overall input-referred offset 5.5 to 4mV Addition of preamp reduces the latch input-referred offset reduced by ~7 to 9X ~extra 3-bit resolution! EECS 247 Lecture 2: Data Converters 26 H.K. Page 56

29 Comparator Preamplifier Gain-Speed Tradeoffs Amplifier maximum Gain-Bandwidth product (f u )for a given technology, typically a function of maximum device f t f =unity gain frequency, f = 3 db frequency & τ = settling time f u fu = = A preamp preamp For example assuming preamp has a gain of : f fu GHz = = = MHz A τ = =.6nsec 2π f A v Magnitude f u =.-GHz Frequency f f u Tradeoff: To reduce the effect of latch offset high preamp gain desirable Fast comparator low preamp gain EECS 247 Lecture 2: Data Converters 26 H.K. Page 57 Latched Comparator f s V i+ A v Latch D o+ V i- D o- Preamp Important features: Maximum clock rate f s settling time, slew rate, small signal bandwidth Resolution gain, offset Overdrive recovery Input capacitance (and linearity of input capacitance!) Power dissipation Input common-mode range and CMR Kickback noise EECS 247 Lecture 2: Data Converters 26 H.K. Page 58

30 Comparators Overdrive Recovery Linear model for a single-pole amplifier: U amplification after time t a During reset amplifier settles exponentially to its zero input condition with τ =RC Assume Vm maximum input normalized to /2lsb (=) Example: Worst case input/output waveforms Previous input max. possible e.g. VFS Current input min. input-referred signal (.5LSB) EECS 247 Lecture 2: Data Converters 26 H.K. Page 59 Comparators Overdrive Recovery Example: Worst case input/output waveforms If trecovery is not high enough to allow output to discharge (recover) from previous state- then it may not be able to resolve the current input error To minimize this effect:. Passive clamp 2. Active restore 3. Low gain/stage EECS 247 Lecture 2: Data Converters 26 H.K. Page 6

31 Comparators Overdrive Recovery Limiting Output Clamp Adds parasitic capacitance Active Restore After outputs are latched Activate φ R & equalize output nodes EECS 247 Lecture 2: Data Converters 26 H.K. Page 6 CMOS Latched Comparator Delay Including Preamplifier Latch delay found previously: C V2 τ D ln g m V Assuming gain of A for the preamplifier: v C V τ D ln Av g m V in EECS 247 Lecture 2: Data Converters 26 H.K. Page 62

32 Latched Comparator Including Preamplifier Example V DD M5 M3 M4 M6 Preamplifier gain: g M3 M3 ( VGS Vth ) ( ) M m v = = M 3 M M gm VGS Vth A + V in - M M2 CLK M9 - V o + Comparator delay: τ C V D ln Av gm Vin bias Preamp M7 Latch M8 EECS 247 Lecture 2: Data Converters 26 H.K. Page 63 Comparator Dynamic Behavior Comparator Reset Comparator Decision CLK T CLK τ delay v OUT EECS 247 Lecture 2: Data Converters 26 H.K. Page 64

33 Comparator Resolution CLK v OUT V IN =mv mv.mv μv Δt = (g m /C).ln(V in /V in2 ) EECS 247 Lecture 2: Data Converters 26 H.K. Page 65 Comparator Voltage Transfer Function Non-Idealities V out ε V Offset -.5LSB.5LSB V in V Offset ε Comparator offset voltage Meta-Stable region (output ambiguous) EECS 247 Lecture 2: Data Converters 26 H.K. Page 66

34 CMOS Comparator Example Flash ADC: 8bits, +-/2LSB fs=5mhz (Vref=3.8V, LSB~5mV) No offset cancellation Ref: A. Yukawa, A CMOS 8-Bit High-Speed A/D Converter IC, JSSC June 985, pp EECS 247 Lecture 2: Data Converters 26 H.K. Page 67 Comparator with Auto-Zero Ref: I. Mehr and L. Singer, A 5-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 999, pp EECS 247 Lecture 2: Data Converters 26 H.K. Page 68

35 Flash ADC Comparator with Auto-Zero V offset V V = V V V C+ C ( + ) Re f Re f Offset Ref: I. Mehr and D. Dalton, A 5-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 999, pp EECS 247 Lecture 2: Data Converters 26 H.K. Page 69 Flash ADC Comparator with Auto-Zero V offset Vo Vo = AP AP2[ ( VIn+ VIn ) ( VC+ VC ) V Offset] Substituting for ( VC+ VC ) from previous cycle: Vo = AP AP2 ( VIn+ VIn ) ( VRe f + VRe f ) Note: Offset is cancelled & difference between input & reference established Ref: I. Mehr and D. Dalton, A 5-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 999, pp EECS 247 Lecture 2: Data Converters 26 H.K. Page 7

Administrative. No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed.

Administrative. No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed. Administrative No office hour on Thurs. this week Instead, office hour 3 to 4pm on Wed. EECS 247 Lecture 2 Nyquist Rate ADC: Architecture & Design 27 H.K. Page EE247 Lecture 2 ADC Converters Sampling (continued)