EE247 Lecture 23. EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 1. Pipeline ADC Block Diagram DAC ADC. V res2. Stage 2 B 2.

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1 EE247 Lecture 23 Pipelined ADCs (continued) Effect gain stage, sub-dac non-idealities on overall ADC performance Digital calibration (continued) Correction for inter-stage gain nonlinearity Implementation Practical circuits Stage scaling Combining the bits Stage implementation Circuits Noise budgeting How many bits per stage? Algorithmic ADCs utilizing pipeline structure Advanced background calibration techniques EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 1 Pipeline ADC Block Diagram ADC DAC - Stage 1 B 1 Bits V res1 Stage 2 B 2 Bits V res2 Stage k B k Bits MSB......LSB Align and Combine Data Digital Output (B 1 B 2..B k ) Bits Idea: Cascade several low resolution stages to obtain high overall resolution (e.g. 10bit ADC can be built with series of 10 ADCs each 1-bit only!) Each stage performs coarse A/D conversion and computes its quantization error, or "residue EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 2

2 Summary So Far Pipelined A/D Converters V ref V ref V ref V ref T/HGain B 1 bits 2 B1eff B 2B2 2 2 bits 2 B2eff B 3 bits 2 B3eff ADC Cascade of low resolution stages By adding inter-stage gain= 2 Beff No need to scale down Vref for stages down the pipe Reduced accuracy requirement for stages coming after stage 1 Addition of Track & Hold function to interstage-gain stages can operate concurrently Throughput increased to as high as one sample per clock cycle Latency function of number of stages & conversion-per-stage Correction for circuit non-idealities Built-in redundancy compensate for sub-adc inaccuracies such as comparator offset (interstage gain: G Bneff, B neff < B n ) EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 3 Pipeline ADC Error Compensation Non-idealities associated with sub-adcs, sub-dacs and gain stages error in overall pipeline ADC performance Need to find means to tolerate/correct errors Important sources of error Sub-ADC errors- comparator offset Gain stage offset Gain stage error Sub-DAC error EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 4

3 Gain Stage Gain Inaccuracy Gain error can be compensated in digital domain "Digital Calibration" Problem: Need to measure/calibrate digital correction coefficient Example: Calibrate 1-bit first stage Objective: Measure G in digital domain EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 5 ADC Model V ref G V in 2 V res1 = G ( V V ) in DAC GV in V V DAC DAC ( D = 0) = 0 ( D = 1) = V ref / 2 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 6

4 Gain Stage Inacurracy Calibration Step 1 V ref = const. - G V res1 (1) Backend D back (1) 1-bit ADC 1 D M U X 1-bit DAC V (1) res1 D (1) back = G = G ( Vin Vref / 2) ( V V / 2) in V ref ref store EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 7 Gain Stage Inacurracy Calibration Step 2 V ref = const. - G V res1 (2) Backend D back (2) 1-bit ADC 0 D M U X 1-bit DAC V (2) res1 D (2) back = G = G ( Vin 0) ( V 0) in V ref store EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 8

5 Gain Stage Inacurracy Calibration Evaluate D D D (1) back (2) back (1) back = G = G D (2) back ( V V / 2) in ( V 0) in V V ref ref ref 1 = G 2 To minimize the effect of backend ADC noise perform measurement several times and take the average EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 9 Accuracy Bootstrapping,ADC Σ ε q1 V res1 V res2 V res(n-1) Σ Σ Σ - G - 1 Σ G - 2 Σ G n-1 ε q2 ε q(n-1) D1 D 2 D (n-1) D n Σ ε qn Σ Σ D out 1/G d1 1/G d2 Σ 1/G d(n-1) D G ε G G = 1 q2 2 q( n 1) ( n 1) qn out Vin, ADC ε q n 2 n 1 Gd1 Gd1 Gd 2 Gd ( n 1) G dj Gdj j= 1 j= 1 Highest sensitivity to gain errors in front-end stages ε ε EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 10

6 "Accuracy Bootstrapping" Direction of Calibration Sufficiently Accurate Stage 1 Stage 2 Stage 3 Stage k B n bits Ref: A. N. Karanicolas et al. "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC," IEEE J. Of Solid-State Circuits, pp , Dec E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs," TCAS II, pp , March 1995 L. Singer et al., "A 12 b 65 MSample/s CMOS ADC with 82 db SFDR at 120 MHz," ISSCC 2000, Digest of Tech. Papers., pp (calibration in opposite direction!) EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 11 Pipeline ADC Errors Non-idealities associated with sub-adcs, sub-dacs and gain stages error in overall pipeline ADC performance Need to find means to tolerate/correct errors Important sources of error Sub-ADC errors- comparator offset Gain stage offset Gain stage error Sub-DAC error EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 12

7 DAC Errors - G V res1 Backend B 1 -bit B 1 -bit ADC DAC D ε DAC D out - 1/G D back Can be corrected digitally as well Same calibration concept as gain errors Vary DAC codes & measure errors via backend ADC EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 13 DAC Calibration Step 1 = const. - G V res1 Backend B 1 -bit ADC D M U X B 1 -bit DAC ε DAC (0) 0 D out 1/G D back ε DAC (0) equivalent to offset - ignore EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 14

8 DAC Calibration Step B1 = const. - G V res1 Backend B 1 -bit ADC D M U X B 1 -bit DAC ε DAC (1...2 B1-1) B1-1 Cal. Register D out 1/G - D back Stepping through DAC codes B1-1 yields all incremental correction values Measurements repeated and averages to account for variance associated with noise EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 15 Pipeline ADC Example: Calibration Hardware Above block diagram may seem extensive however, in current fine-line CMOS technologies digital portion of a pipeline ADCs consume insignificant power and area compared to the analog sections Ref: E. G. Soenen et al., "An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs," TCAS II, pp , March 1995 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 16

9 Pipelined ADC Error Correction/Calibration Summary V OS a 3 V 3 V IN1-2 3 V RES1 ADC DAC ε gain ε ADC ε DAC D 1 Error ε ADC, V os ε gain ε DAC Inter-stage amplifier non-linearity Redundancy either same stage or next stage Digital adjustment Correction/Calibration Either sufficient component matching or digital calibration? EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 17 Inter-stage Gain Nonlinearity Invert gain stage non-linear polynomial Express error as function of V RES1 Push error into digital domain through backend Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue Amplification," ISSCC Dig. Techn. Papers, pp , 2003 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 18

10 a 3 V X 3 Inter-stage Gain Nonlinearity V X 2 3 ε gain V RES1 Backend p 2 D B a = (2 ε gain ) (...) D B,corr - ε(d B, p 2 ) ε(db,p2) = p2db 3p2 DB 12p2 DB... Pre-computed table look-up p 2 continuously estimated & updated (account for temp. & other variations) Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue Amplification," ISSCC Dig. Techn. Papers, pp , EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 19 Inter-stage Gain Nonlinearity Compensation Proof of Concept Evaluation Prototype Re-used 14-bit ADC in 0.35μm from Analog Devices [Kelly, ISSCC 2001] Modified only 1 st stage with 3-b eff open-loop amplifier built with simple diff-pair resistive load instead of the conventional feedback around high-gain amp Conventional 9-b eff backend, 2-bit redundancy in 1 st stage Real-time post-processor off-chip (FPGA) Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue Amplification," ISSCC Dig. Techn. Papers, pp , 2003 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 20

11 Measurement Results 12-bit ADC w Extra 2-bits for Calibration (a) without calibration INL [LSB] RNG=0 RNG= Code (b) with calibration (b) with calibration INL [LSB] Code C d EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 21 Combining the Bits Example: Three 2-bit stages, no redundancy B 1 B 1eff B 2 B 2eff B 3 Stage 1 Stage 2 Stage D D 2 D 3 D out 1/2 2 1/ Dout = D1 D 1 2 B eff B1eff B2eff Dout = D1 D2 D D3 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 22

12 Combining the Bits D 1 XX D 2 XX D 3 XX D out DDDDDD Only bit shifts No arithmetic circuits needed B 1 B 1eff B 2 B 2eff B 3 Stage 1 Stage 2 Stage 3 D 1 D 2 D 3 MSB LSB D out[5:0] EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 23 Combining the Bits Including Redundancy Example: Three 2-bit stages, incorporating 1- bit redundancy in stages 1 and 2 B 1 =3 B 1eff B 2 =3 B 2eff B 3 Stage 1 Stage 2 Stage 3 8 Wires??? 6 Wires D out[5:0] EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 24

13 Combining the Bits 1 1 Dout = D1 D 1 2 D B eff B1eff B2eff Dout = D1 D2 D B 1 =3 B 1eff B 2 =3 B 2eff B 3 Stage 1 Stage 2 Stage 3 D 1 D 2 D 3 Bits overlap Need adders D 1 XXX D 2 XXX D 3 XX D out DDDDDD HADD HADD FADD HADD HADD D out[5:0] EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 25 Combining the Bits Example B 1 =3 B 1eff B 2 =3 B 2eff B 3 Stage 1 Stage 2 Stage 3 D 1 D 2 D 3 D D D D out HADD HADD FADD HADD HADD D out[5:0] EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 26

14 Stage Implementation CLK φ 1 φ 1 φ 2 φ 1... φ 2 acquire convert convert acquire Stage 1 Stage 2 Stage n T/H - G V res ADC DAC Each stage needs T/H hold function Track phase: Acquire input/residue from previous stage Hold phase: sub-adc decision, compute residue EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 27 Stage Implementation T/H T/H - G V res T/H ADC DAC Usually no dedicated T/H amplifier in each stage (Except first stage in some cases why?) T/H implicitely contained in stage building blocks EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 28

15 Stage Implementation T/H - G V res T/H ADC DAC MDAC DAC-subtract-gain function can be lumped into a single switched capacitor circuit "MDAC" EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page Bit Stage Implementation Example D1,D0 V DAC Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis, 1999 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 30

16 1.5-Bit Stage Implementation Acquisition Cycle Φ 1 D1,D0 V DAC Vc f =Vc s =V i Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis, 1999 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 31 Φ Bit Stage Implementation Conversion Cycle D1,D0 V DAC Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis, 1999 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 32

17 1.5 Bit Stage Implementation Example Note: Interstage gain set by C ratios Accuracy better than 0.1% Up to 10bit level no need for gain calibration Ref: A. Abo, "Design for Reliability of Low- voltage, Switched-capacitor Circuits," UCB PhD Thesis, 1999 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page Bit Stage Implementation Timing of Stages V DAC V DAC Conversion Acquisition EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 34

18 Pipelined ADC Stage Power Dissipation & Noise Typically pipeline ADC noise dominated by inter- stage gain blocks Sub-ADC comparator noise translates into comparator threshold uncertainty and is compensated for by redundancy Stage 1 Stage 2 Stage 3 V n1 G1 G2 G3 V n2 V n3 2 2 in 2 V n2 V V n3 noise = V n G1 G1 G2 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 35 Pipelined ADC Stage Scaling Example: Pipeline using 1-bit eff stages V n1 G1 G2 G3 V n2 V n3 C 1 /2 C 2 /2 C 3 /2 C 1 Gm C 2 Gm C 3 Gm Total input referred noise power: Ntot kt... C G1 C2 G1 G2 C Ntot kt... C1 4C2 16C3 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 36

19 Pipelined ADC Stage Scaling C 1 /2 C 2 /2 C 3 /2 C 1 Gm C 2 Gm C 3 Gm N tot kt... C1 4C2 16C3 If all caps made the same size, backend stages contribute very little noise Wasteful power-wise, because: Power ~ Gm Speed ~ Gm/C Fixed speed Gm/C filxed Power ~ C EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 37 Pipelined ADC Stage Scaling C 1 /2 C 2 /2 C 3 /2 C 1 Gm C 2 Gm C 3 Gm N tot kt... C1 4C2 16C3 How about scaling caps down by G 2 2 =4x per stage? Same amount of noise from every stage All stages contribute significant noise To keep overall noise the same noise/stage must be reduced Power ~ Gm ~ C goes up! EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 38

20 Stage Scaling Example: 2-bit eff /stage Optimum capacitior scaling lies approximately midway between these two extremes Ref: D. W. Cline, P.R. Gray "A power optimized 13-b 5MSamples/s pipelined analog-to-digital converter in 1.2um CMOS," JSSC 3/1996 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 39 Pipeline ADC Stage Scaling Power minimum is "shallow Near optimum solution in practice: Scale capacitors by stage gain E.g. for effective stage resolution of 1bit (Gain): C/2 C/4 C/8 C Gm C/2 Gm C/4 Gm EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 40

21 Stage Scaling Example Note: Resolution per stage: 2bits A=4 Ref: D. W. Cline, P.R Gray "A power optimized 13-b 5 MSamples/s pipelined analog-to-digital converter in 1.2um CMOS," JSSC 3/1996 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 41 How Many Bits Per Stage? Many possible architectures E.g. B 1eff =3, B 2eff =1,... vs. B 1eff =1, B 2eff =1, B 3eff =1,... Complex optimization problem, fortunately optimum tends to be shallow... Qualitative answer: Maximum speed for given technology Use small resolution-per-stage (large feedback factor) Maximum power efficiency for fixed, "low" speed Try higher resolution stages Can help alleviate matching & noise requirements in stages following the 1 st stage Ref: Singer VLSI 96, Yang, JSSC 12/01 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 42

22 14 & 12-Bit State-of-the-Art Implementations Reference Bits Architecture SNR/SFDR Speed Power Yang (JSSC 12/2001) 0.35μ/3V ~73dB/88dB 75MS/s 340mW Loloee (ESSIRC 2002) 0.18μ/3V ~66dB/75dB 80MS/s 260mW EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page & 8-Bit State-of-the-Art Implementations Reference Bits Architecture SNR/SFDR Speed Power Yoshioko et al (ISSCC 2005) 0.18μ/1.8V bit/stage ~55dB/66dB 125MS/s 40mW Kim et al (ISSCC 2005) 0.18μ/1.8V ~48dB/56dB 200MS/s 30mW EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 44

23 Algorithmic ADC Digital Output start of conversion Shift Register & Correction Logic Residue V IN T/H sub-adc (1.6 Bit) DAC 2 B Essentially same as pipeline, but a single stage is reused for all partial conversions For overall B overall bits need B overall /B stage clock cycles per conversion Small area, slow EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 45 Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters Slow, but accurate ADC operates in parallel with pipelined (main) ADC Slow ADC samples input signal at a lower sampling rate (f s /n) Difference between corresponding samples for two ADCs (e) used to correct fast ADC digital output via an adaptive digital filter (ADF) based on minimizing the Least-Mean-Squared error Ref: Y. Chiu, et al, Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters, IEEE TRANS. CAS, VOL. 51, NO. 1, JANUARY 2004 EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 46

24 Example: "A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration" Pipelined ADC operates at has 1.5bit/stage Slow ADC Algorithmic type operating at 20Ms/32=625ks/s Digital correction accounts for bit redundancy Digital error estimator minimizes the mean-squared-error Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 47 Algorithmic ADC Used for Calibration of Pipelined ADC (continued from previous page) Uses replica of pipelined ADC stage Requires extra SHA in front to hold residue Undergoes a calibration cycle periodically prior to being used to calibrate pipelined ADC Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 48

25 12-bit 20-MS/s Pipelined ADC with Digital Background Calibration Sampling capacitors scaled: Input SHA: 6pF Pipelined ADC: 2pF,0.9,0.4,0.2, 0.1,0.1 Algorithmic ADC: 0.2pF Chip area: 13.2mm 2 Area of Algorithmic ADC <20% Does not include digital calibration circuitry estimated ~1.7mm 2 Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 49 Measurement Results 12-bit 20-MS/s Pipelined ADC with Digital Background Calibration Without Calibration INL <4.2LSB With Calibration INL <0.5LSB Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 50

26 Measurement Results 12-bit 20-MS/s Pipelined ADC with Digital Background Calibration Nyquist rate Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 51 Measurement Results 12-bit 20-MS/s Pipelined ADC with Digital Background Calibration Does not include digital calibration circuitry estimated ~1.7mm 2 Alg. ADC SNDR dominated by noise Ref: X. Wang, P. J. Hurst, S. H. Lewis, " A 12-bit 20-MS/s pipelined analog-to-digital converter with nested digital background calibration, IEEE JSSC, vol. 39, pp , Nov EECS 247 Lecture 23 Pipelined ADCs 2008 H.K. Page 52