International Journal of Advanced Research in Computer Science and Software Engineering

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1 Volume 3, Issue 1, January 2013 ISSN: X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: Low Power High Speed 4 Bit Resolution Pipeline ADC Design in Submicron CMOS Technology Ms. Rita M. Shende Dept of E.X.T.C. Sipna C.O.E.T.Amravati University, Maharashtra, India Prof. P. R. Gumble Dept of E.X.T.C. Sipna C.O.E.T.Amravati University, Maharashtra, India Abstract- Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. Wide spread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). This has recently generated a great demand for low-power, low-voltage ADCs that can be realized in a mainstream deep-submicron CMOS technology. Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption. This paper presents a 4 bit Pipeline ADC with low power dissipation implemented in <0.18μm CMOS technology with a power supply of 1.2V. Keywords: Analog-to-digital converter (ADC), CMOS circuits I. INTRODUCTION As IC fabrication technology has advanced, more analog signal processing functions have been replaced by digital blocks,analog-to-digital converters (ADCs) retain an important role in most modern electronic systems because most signals of interest are analog in nature and must to be converted to digital signals for further signal processing in the digital domain. There is wide variety of different ADC architectures available depending on the requirements of the application. Pipeline ADCs are one of the best examples. Pipeline analog to-digital converters (Pipeline ADC) have recently become very attractive in energy efficient moderate-resolution/moderate-speed applications due to their minimal active analog circuit requirements. It typically generate one bit per clock cycle, the benefits are the low area needed for the implementation. ADCs of this type have good resolutions and quite wide ranges. By combining the merits of the successive approximation and flash ADCs this type is fast, has a high resolution, and only requires a small die size. The pipeline analog-to-digital converter (ADC) is a promising topology for high-speed data conversion with compact area and efficient power dissipation. Its speed of operation far surpasses that of serial-based structures, such as successive approximation or cyclic converters, while its die area and power dissipation favorably compare to that of flash and other more parallelized architectures. Pipelined ADCs are widely used in the areas of wireless communications, digital subscriber line analog front ends, CCD imaging digitizers, studio cameras, ultrasound monitors, and many other high speed applications. Pipeline analog-to-digital converters (ADC S ) represent the majority of the ADC market for medium-to highresolution ADC S. Pipeline ADC S provide up to 5Msps sampling rates with resolutions from 8 to 18 bits. The Pipeline ADC architecture allows for high performance, low power ADC S to be packaged in small form factors for today s applications. With ADC we have designed 4 bit low power high speed Pipeline ADC with 0.18μm technology. II. REWIEW OF WORK The first documented example of an ADC was a 5-bit, electro-optical and mechanical flash-type converter patented by Paul Rainey in 1921, used to transmit facsimile over telegraph lines with 5-bit pulse-coded modulation (PCM). The first all-electrical implementation came in 1937 by Alec Harvey Reeves, this also had a 5-bit resolution and the ADC was implemented by converting the input signal to a train of pulses which was counted to generate the binary output at a sample rate of 6 ks/s. Following this the successive approximation ADC was developed in 1948 by Black, Edson Goodall to digitize voice to 5-bits at 8 ks/s. Also in 1948, a 96 ks/s, 7-bit ADC was developed and it was developed and it was implemented using an electron beam with a sensor placed on the other side of a mask. The mask had holes patterned according to the binary weights so that all bits were simultaneously detected, the pattern also employed Gray coding of the output in order to reduce the effect of errors in the most significant bit (MSB) transition, much as is done in modern high-speed flash ADC S [12]. 2013, IJARCSSE All Rights Reserved Page 189

2 Following the development of the transistor in 1947 and the integrated circuit in 1958, the ADC development continued in the 1960 s with for example an 8-bit, 10 MS/s converter that was used in missile-defence programs in the United States. During the same decade, all the currently used high-speed architectures were developed including Pipeline ADC S with error correction. Commercial flash converters appeared in instruments and modules of the 1960 S and 1970 S and quickly migrated to integrated circuits during the 1980 S. The monolithic 8-bit flash ADC became an industry standard in digital video applications of the 1980 S. Today, the flash converter is primarily used as a building block within subranging pipeline [9]. Using Partial amplifier sharing topology, a 6-bit pipeline ADC, developed in 0.35μm CMOS process. A 6-bit, 2.5 V flash ADC design has been reported new flash topology and this new topology has only 2(N-2) + 2 comparators required. Here area of the chip is large and its required to minimize it [10]. The AD7880 is a high speed, low power, 12-bit A/D converter which operates from a single +5V supply. First commercial converter, 1954 "DATRAC" 11-Bit, 50-kSPS SAR ADC Designed by Bernard M. Gordon at EPSCO. In the recent years there has been a trend in ADC research to use low accuracy analog components which are compensated for through the use of digital error correction. Because of their popularity, successive approximation ADCs are available in a wide variety of resolutions, sampling rates, input and output options, package styles, and costs. Many SAR ADCs now offer on-chip input multiplexers, making them the ideal choice for multichannel data acquisition system. An example of modern charge redistribution successive approximation ADCs is Analog Devices' PulSAR series. TheAD7641 is a 18-bit, 2-MSPS, fully differential, ADC that operates from a single 2.5 V power supply. The part contains a high-speed 18-bit sampling ADC, an internal conversion clock, error correction circuits, internal reference, and both serial and parallel system interface ports. The AD7641 is hardware factory calibrated and comprehensively tested to ensure such ac parameters as signal-to-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offset, and linearity. The motivation behind this is that analog design have not been able to benefit from process scaling in the same way as digital logic and therefore the relatively area cheap digital logic is used to compensate for the shortcomings of expensive analog circuits. For device reliability reasons, the supply voltage needs to be reduced to ensure gate oxide integrity over time and prevent p-n junction from breakdown. Present-day CMOS processes are making the transition from 3.3 V to 1.8 V supplies. The converter should operate with high sampling rate from an operating supply as low as possible, to facilitate integration with low-voltage, power efficient digital circuits. III. PIPELINE ADC DESIGN The pipeline ADC architecture combines the benefits of high throughput and an input capacitance bound by noise constraints. Typical pipeline architecture is illustrated in Figure 1. Each stage has the four elements of Comparator, a summer, multiplier, mux and transmission gate. Fig 1 pipeline A/D converter The pipeline ADC is an N-step converter, with 1 bit being converted per stage. Able to achieve high resolution (10-13 bits) at relatively fast speeds, the pipeline ADC consists of N stages connected in series (Fig.). Each stage contains a 1-bit ADC (a comparator), a sample-and-hold, a summer, and a gain of two amplifiers. Each stage of the converter performs the following operation: 1. After the input signal has been sampled, compare it to vref/2. The output of each comparator is the bit conversion for that stage. 2. If vm > vref/2 (comparator output is 1), vref/2 is subtracted from the held signal and pass the result to the amplifier. If vin < vref/2 (comparator output is 0), then pass the original input signal to the amplifier. The output of each stage in the converter is referred to as the residue. 3. Multiply the result of the summation by 2 and pass the result to the sample and- hold of the next stage. 2013, IJARCSSE All Rights Reserved Page 190

3 A main advantage of the pipeline converter is its high throughput. After an initial latency of N clock cycles, one conversion will be completed per clock cycle. While the residue of the first stage is being operated on by the second stage, the first stage is free to operate on the next samples. Each stage operates on the residue passed down from the previous stage, thereby allowing for fast conversions. The disadvantage is having the initial N clock cycle delay before the first digital output appears. The severity of this disadvantage depends, of course, on the application. One interesting aspect of this converter is its dependency on the most significant stages for accuracy. A slight error in the first stage propagates through the converter and results in a much larger error at the end of the conversion. Each succeeding stage requires less accuracy than the one before, so special care must be taken when considering the first several stages. The Pipelined ADC can be thought of as an amplitude- interleaved topology where errors from one stage are correlated with errors from previous stage. The basic block diagram implementation of an N-bit Pipelined ADC using the cyclic stages is as shown in Figure 2. Instead of cycling the analog output of the 1 bit/stage section back to its input, we feed the output into next stage. The stages are clocked with opposite phases of the master clock signal. The comparator outputs are labelled digital in figure. Fig 2. Pipeline ADC based on cyclic stages The digital comparator outputs are delayed through latches so that the final digital output word corresponds to the input signal sampled N clock cycles earlier. The first stage in figure must be N-bit accurate. It must amplify its analog output voltage, VN-1 to within 1 LSB of the ideal value. The second stage output, VN-2 must be an analog voltage within 2 LSB of its ideal value. The third stage output, VN-3 must be an analog voltage within 4 LSB of its ideal value. Power dissipation in ADC Power dissipation in CMOS logic arises from following 1) Switching current from charging and discharging parasitic capacitance. 2) Short circuit current when both N & P channel transistors are momentarily on at the same time. 3) Leakage current & subthreshold current. Average dynamic power dissipated is given by :- Pavg =Ctot * VDD 2 *Fclk Notice that power dissipation is a function of clock frequency. A great deal of effort is put into reducing the Power dissipation in CMOS circuits. Together with the scaling of process geometry, the supply voltage (squared term) is reduced in order to both reduce the digital Power dissipation and the rate of device degradation. Also we have to reduce short circuit current, subthreshold current, leakage current. The basic problems coupled to SC, such as clock feedthrough from digital part through the switches, capacitor mismatch and op-amp non-idealities, have been taken into account during the design of the ADC. AS we are using 0.18μm technology, supply voltage is 1.2 V. Also due to clock redundancy Power dissipation is reduced. IV. CIRCUIT IMPLEMENTATION With ADS and various designed components we have designed complete Pipeline Architecture shown in fig 3. And we got the simulation results shown in fig 4. And table 1 shows digital values for given analog voltage. 2013, IJARCSSE All Rights Reserved Page 191

4 Fig 3 Pipeline Architecture For our Design of 4 bit resolution ADC digital code we are getting is as follows Table 1 Digital Codes Input analog Q3 Q2 Q1 Q0 voltage , IJARCSSE All Rights Reserved Page 192

5 tv, V a3, V a2, V a1, V as0, V bin3, V bin2, V bin1, V bin0, V Rita et al., International Journal of Advanced Research in Computer Science and Software Engineering 3(1), Simulation Results time, nsec time, nsec Fig 4 Simulation Results for Pipeline ADC The ADC is fabricated in 0.18μm standard CMOS process with 4 bit rsolution. The value of the unit capacitor is 100fF. The static performance of the ADC is shown in Fig. 3. ADC operats at 1.2v. The DNL and INL of the ADC are a measurement factor of linearity.. Pipeline ADC vs other ADCs Power dissipation of Pipeline ADCs varies with the sampling rate unlike Flash and SAR architectures. Hence find applications in PDAs. The SAR ADC's are low power consumption, high resolution, and accuracy. In a SAR ADC, increased resolution comes with the increased cost of more-accurate internal components. Flash ADC is much faster, less accurate and takes more silicon area due to the number of comparators 2N for N bit 2013, IJARCSSE All Rights Reserved Page 193

6 resolution. Oversampled/Σ-J ADCs have low conversion rates, high precision, averaging noise and no requirement for trimming or calibration even up to 16 bits of resolution. V. CONCLUSION ADC is the key design Block in modern microelectronics digital communication system. With the fast advancement of CMOS fabrication technology and continued proliferation of mixed analog and digital VLSI systems, the need for small sized, low-power and high-speed analog-to-digital converters has increased. With an increasing trend to a system-on-chip, an ADC has to be implemented in a low-voltage submicron CMOS technology in order to achieve low manufacturing cost while being able to integrate with other digital circuits. So we have proposed low power ADC. From different ADC architectures available Flash ADC is having the drawback of large chip area n high power dissipation and Pipeline ADC has complex circuit. The Pipeline ADC is best suitable for low power application. For designing purpose we have used Advanced Designing System. The Pipeline ADC core is composed by comparator, Transmission Gate, and pipeline control logic; these components have been designed targeting to fulfill several constraints on requirements such as low power dissipation, the offsets due to mismatch. From the results presented we could conclude that conversion is performed without missing codes and a low-power high speed 4-bit Pipeline ADC in a 0.18μm CMOS process with a 1.2 V supply voltage is designed. REFERENCES [1] Baker, R. Jacob, Li, Harry W., Boyce, David E., CMOS Circuit Design, Layout, and Simulation, 1st on edition (IEEE Press Series on Microelectronic Systems) [2] Stephen H. Lewis and Paul. Gray, A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter, IEEE J. Solid- State Circuits, vol. 22, issue.12,pp , Dec [3] Razavi, Behzad; Principles of Data Conversion System Design; IEEE Press, [4] A. M. Abo and P. R. Gray, A -V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter, IEEE J. Solid- State Circuits, vol. 34, no. 5, pp , May [5] T. Stockstad and H. Yoshizawa, "A 0.9-V ma Rail-to-Rail CMOS Operational Amplifier," IEEE Journal of Solid-State Circuits, vol. 37, pp , [6] N. Verma and A. P. chandrakasan, A 25uW 100kS/s 12b ADC for wireless micro-sensor applications, IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp , [7] Circuit Design Techniques for low-voltage high-speed A/D converters, by Mikko Waltari; Distributed by Helsinki University of Technology,2002. [8] Dwight U. Thomson and Bruce A. Wooley, A 15-b pipelined CMOS floating point A/D converter, Journal of IEEE Solid State Circuit,vol. 36, no. 2, February [9]R. Samer and Jan Van der Speigel and K. Nagaraj, Background digital error correction technique for pipeline ADC, IEEE, [10] A. Shabra and Hae-Seung Lee, Oversampled pipelined A/D converter with mismatch shaping, Journal of IEEE Solid State Circuit, vol. 37, no. 5, May2002.Makalah /1937/5/methodology.pdf,may2007 Edition, Oxford University Press, Oxford, ISBN , (2002). [11] S H Lewis, P. H. Gray A pipelined 5-Msampled/s 9-bit Analog-to digital converter.", JSSC, December 1987 [12] Timmy Sundstrom, Design of high-speed, Low-Power, Nyquist Analog-to-Digital Converters, Thesis No. 1423, ISBN ISSN [13]Van De Plassche, Rudy; Integrated Analog-to-Digital and Digital-to-Analog Converters; Kluwer Academic Publishers, [14] Siddharth Devarajan and Larry Singer, A 16-bit, 125 MS/s, 385 mw, 78.7 db SNR CMOS Pipeline ADC, IEEE J. Solid-State Circuits, vol. 44, No.12, pp , Dec [15] A Crash Course on using Agilent Advanced Design System (ADS) By Chris sanabria, sanabria@ece.ucsb.edu [16] Chang-Hyuk Cho, A POWER OPTIMIZED PIPELINED ANALOG-TO-DIGITAL CONVERTER DESIGN IN SUB-MICRON CMOS TECHNOLOGY A Thesis Presented, Dec [17] Y. Chiu, P. R. Gray, and B. Nikolic, A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR, IEEE J.Solid-State Circuits, vol. 39, No. 12, pp , Dec , IJARCSSE All Rights Reserved Page 194