Simulation of High Performance Pipelined ADC Based on Optical Component Using VHDL

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1 Simulation of High Performance Pipelined ADC Based on Optical Component Using VHDL Kavita chourasia, Abhishek Choubey, Sudhir kumar Abstract This thesis explores the high performance ADC based on optical component. This research work presents a two stage pipelined ADC that is basically a broadband high sampling rate,high resolution and high speed application. which incorporates a Flash ADC using optical components like optical source and optical detector. The application of this methodology not only enhanced sampling rate but also minimizes the power consumption and hardware of the structure. Traditionally, electronic component based flash ADC were used, but the drawback with such ADC was the increased propagation delay and low resolution. To get rid of this drawback, in this research work the electronic component are replaced by optical source and array of optical detectors. In this thesis the comparison of electronic component based pipelined ADC with optical component based pipelined ADC is shown. For evaluation of the parameter VHDL code is implemented the analysis results are shown that our analog to digital converter scheme is promising to achieve high resolution of up to 12 bit at the sampling rate of approximate 8 GSPS. Index Terms ADC, Flash ADC, Pipelined Architecture, Optical Component, Subranging ADC VHDL I. INTRODUCTION ADCs and Digital to Analog Converters (DACs) are well-known and very important features in modern day electronics. The applications of data converters vary greatly from TV tuner cards to digital oscilloscopes and software-defined radio. The advancements in digital signal processing and digital hardware mean that more traditional analog functions of devices such as radio have been replaced by software or digital hardware. Area, power and speed are important parameter for ADC for integrated on large digital IC s. Several ADC architectures are capable of achieving these specification e.g. flash ADC, pipeline ADC, folding ADC and sub ranging ADC. However, when small area low power operation are of primary importance, the pipelined architecture and sub ranging architecture has proven to be a very suitable choice. Comparator is the most critical circuit in a flash ADC. but because of comparator there are many drawback in the results and it consume more power.. So this problem of comparator can be removed by eliminating the comparator. this block of comparator, has used in simple flash ADC is replaced by the another block that consist of optical source and optical detector[1]. This block plays same role as comparator. This block of optical array consume less chip area because of its small size and provide high speed,when it implemented on hardware. as we know the GaAsP based technology will be most significant in the area of ultra high speed application. so in this paper we are using LED of GaAsP semiconductor material as optical source with 1.8 nsec that is less than comparator delay. Several ADC architecture have been proposed that try to keep the same high sampling speed of the flash converter. However the parallelism of flash architecture causes several problem for high resolution. So the higher resolution ADC can be obtained by pipelined architecture of flash ADC[2]. this pipeline architecture of ADC is limited to speed up to some MHz, so by using pipelining of optical detector based flash type ADC, speed can be increased up to several GHz with sampling rate GS/s. By using these concept described above this paper proposing a new architecture high performance pipelined optical ADC. To reduce the power consumption this technique decrease the number of comparator required. The ADC achieves an effective resolution greater 8 bit at sampling rate of 10 GS/s. while consuming less power than comparator because of small size of GaAsP based LED and optical detector. In this work the design implementation of pipelined ADC based on optical detector is presented and then simulation is carried out by, XILINX and Modelsim. II. SPEED IMPROVING METHODS OF ADC There are many approaches to implementing high speed ADC these are : Parallel pipeline with multiple- bit/stage, Pipeline Flash ADC folding and interpolation digital error correction but in this paper we are using only pipelining architecture A. Two stage pipelined flash ADC 6

2 The pipelined (or pipelined-flash) architecture effectively overcomes the limitations of the flash architecture Pipeline ADCs[5]..It provide the high resolution and sampling rate to cover a wide range of applications, including CCD imaging, ultrasonic medical imaging, digital video (for example, HDTV), XDSL, and fast Ethernet. software radio, base stations, and set-top boxes and consumer electronics equipment, such as digital cameras, display electronics, DVDs, enhanced definition TVs, and high-definition TV. The Origins of Pipeline ADCs is Flash ADC and Sub-Ranging ADCs. The principle of sub-ranging ADC can be pushed to the limit of having only one bit per stage, At this point, each flash ADC is nothing more than a simple comparator, Also, the data is transferred in a pipeline fashion: when the data is sent to the second stage, another sampled data is fed to the first stage, The result is a latency delay equal to the number of stages. For sampling rates greater than approximately 5 MSPS, the pipelined architecture dominates. These applications typically require resolutions up to 14 bits with high SFDR and SNR at sampling frequencies ranging from 5 MSPS to greater than 100 MSPS. The pipelined ADC has its origins in the subranging architecture, first used in the 1950s. In order to increase the speed of the basic subranging ADC, the pipelined architecture shown in figure:1 represents one bit of the overall word. Each comparator has its own threshold voltage, spaced by1 LSB, The input is fed to all the comparators in parallel, The output of the comparators is in thermometer format, An encoder is used to convert to binary format. They are often used for video and other fast signals. The parallelism of the comparators allows for the high speed. The speed capability of the flash architecture ranges from MSPS for 4 to 8 bits of resolution[3]. The major problem with this type of ADC is its sheer volume. The number of comparators needed for resolution of n-bits is equal to 2 n -1. This is why flash resolutions stay below 10-bits thus limiting it to applications requiring high speed and low resolution such as video applications. For 8-bits of resolution 255 comparators are needed. Figure 2 shows a n-bit flash ADC. This input bank of comparators provides a very high input capacitance, which requires an equally high current to drive them all sufficiently. Figure 2 : n-bit Flash ADC Figure 1 : Two stage pipelining architecture This pipelined ADC has a digitally corrected subranging architecture in which each of the two stages operates on the data for one-half of the conversion cycle, and then passes its residue output to the next stage in the pipeline prior to the next phase of the sampling clock. The inter stage track-and-hold (T/H) serves as an analog delay line it is timed to enter the hold mode when the first-stage conversion is complete. This allows more settling time for the internal SADCs, SDACs, and amplifiers, and allows the pipelined converter to operate at a much higher overall sampling rate than a non pipelined version [2]. B. Optical Component Based flash ADC The highest speed ADC is the flash ADC. This Flash ADC provides the highest conversion rate of all the ADC architectures for a given technology. It consists of a bank of comparators feeding into a logic circuit. Each comparator Since comparator based flash ADC has a problem of lower sampling rate, large propagation delay and more power consumption. So The problem associated with conventional flash ADC can be minimized by using high speed component. For achieving high performance flash ADC, we are replacing the comparator with high speed component. Here we are using optical component as a high speed component. these components are optical source and array of optical detector. The combination of optical source and optical detectors array work s as optical coupler. The optical component has a advantages of small size, low power consumption, and fast response time of few nanosecond [14]. The configuration of the flash ADC based on optical component is depicted in fig 3 shown below. The optical source converts the electrical signal into a optical frequency and optical detector detect optical frequency and convert it into a electrical signal of a fixed amplitude of corresponding frequency. In each positive edge of CLK sample and hold circuit take new sample of analog input. These samples are fed in optical source1. Since optical source and detector have fast switching speed as compare to electronic 7

3 comparator hence for improving speed of ADC we use optical source-detector pair.. According to input voltage optical source (Laser) produce different freq sample. Figure 3 : flash ADC based on optical components These frequency samples are fed in optical detector block. When any optical frequency matched with frequency range of optical detector range then that optical detector produce output high voltage or logic1 (in digital) other detector produce low voltage or logic zero. These outputs of optical detector acts as a input of encoder. According to these input (optical detector s output) encoder produce output bit unique code which is ADC digital output. C. Subranging ADC The subranging ADC limits the problems of flash ADC.This ADC has many advantages over flash ADC. The subranging ADC require less hardware as compare to flash ADC for example 6-bit flash ADC require 63 comparator but 6-bit two stage subranging ADC require only 14 comparator.this ADC also require lower power dissipation, smaller input capacitance[4]. The configuration of a simple 6-bit, two-stage subranging ADC is shown in Figure[4] The output of the S&H is digitized by the first-stage simple 3-bits flash ADC, The digital value is converted back in analog format by a 3-bit DAC and subtracted from the input, this gives a residue, The residue is multiplied to get the full range, and then converted by a second stage 3-bit flash ADC to generate the three LSBs of the total 6-bit output word. But there is a disadvantage with subranging ADC is that its Hardware Still Increases Exponentially within Each Flash ADC.Using all these techniques discussed above we can design high performance ADC based on optical component for increasing high speed,high resolution and high sampling rate with less hardware requirement. The high performance ADC is explained in the next section. III. HIGH PERFORMANCE ADC BASED ON OPTICAL COMPONENT This schemes are proposed and investigated to overcome the inherently limitation of comparator or electronic ADC. The configuration of the high performance ADC based on optical component is depicted in fig 1 which is made from a pulsed laser and array of optical detectors using as a optical components,this combination makes opto-coupler and the 6 bit two stage pipelined architecture for high speed application and high sampling rate is shown below. Figure5: architecture of high performance ADC based on optical component Figure 4 : 6 bit two-stage subranging ADC This architecture provide high sampling rate and high speed using pipelining architecture.the design of multi bit flash ADC is achieved by cascading a number of n bit flash ADC modules. Here we are presenting 6 bit high performance ADC. this is achieved by cascading implementation of two module of 3 bit flash ADC.In order to increase the speed of the basic subranging or cascading ADC, the pipelining architecture is used,this uses a analog delay or delay element the pipelined architecture in which each of the two stages operates on the data 8

4 for one-half of the conversion cycle, and then passes its residue output to the next stage in the pipeline prior to the next phase of the sampling clock. The inter stage analog delay line it is timed to enter the hold mode when the first-stage conversion is complete. This allows more settling time for the internal flash ADCs, DACs, and amplifiers, and allows the pipelined converter to operate at a much higher overall sampling rate than a nonpipelined version In each positive edge of CLK sample and hold circuit take new sample of analog input. These samples are fed in optical source1 and delay circuit. Since optical source and detector have fast switching speed as compare to electronic comparator hence for improving speed of ADC we use optical source-detector pair. Optical sources are fast and consume less power. According to input voltage optical source (Laser) produce different freq sample. These frequency samples are fed in optical detector block. When any optical frequency matched with frequency range of optical detector range then that optical detector produce output high voltage or logic1 (in digital) other detector produce low voltage or logic zero. These outputs of optical detector acts as a input of 7 X 3 encoder1. According to these input (optical detector s output) encoder1 produce 3 bit unique code which is MSB (5 th to 3 rd ) of ADC digital output.these 3 bit of encoder1 are fed into 3 bit resolution DAC means DAC give 8 different level of analog output. The output of DAC are fed to the inverting terminal of OP_AMP (pin no 2). The Delayed sample of analog input are fed into the non inverting terminal of op-amp (pin no 3). The gain of the op-amp depends upon n bit ADC where n is the number of output bits, In this case the gain is 8 (2 3 ), as we have used 3-bit ADC. Optical source2 must have same characteristics as optical source 1 because if optical sources are same then we can use same optical detector block2. It is easy to fabricate same optical source detector block in a particular chip. Now same processes are repeated for second stage. Second stage gives the 3 lowest significant bit (2,1,0) of digital output of ADC. In this way we require only 14 optical detector, 7 detector in each stage in place of 63 (2 6-1 ) detector. The first encoder outputs MSB bits are stored and use as a final output with LSB. So when the second stage of previous input is encoded we can take new sample in first stage in this manner this architecture worked in pipelined fashion and this pipelined architecture again enhance speed of operation. Snapshot1.Output waveform of ADC 9

5 Snapshot2 Comparison of conversion time 1. conversion time electronic component based ADC Snapshot 3: Conversion time of optical component based ADC Snapshot 4: Comparison of propagation delay 10

6 1. Propagation delay time of electronic component based ADC 11

7 2. Propagation Delay Time of Optical component based ADC S. NO Parameter Electronics component based ADC 1280psec Table A. Comparison for Various Components 1 Sampling 556 MSPS ~8GSPS rate 2 No. of detector required Table B.Comparison between Pipelined and Non pipelined ADC Using time-interleaved technology already has been reported in [17]. A series of light pulses with frequency of 150 GHz obtained by the Therefore, the Proposed ADC of our scheme has potential to obtain high-speed sampling at the rate of 150 GS/s IV. CONCLUSION Optical component based ADC 120psec 1 Conversion time 2 Delay time 2980psec 1850psec 3 Sampling rate 833MSPS ~ 8GSPS S.NO Parameter Optical component based 6-bit ADC Optical component based 6-bitADC with pipelining We present a high performance pipeline ADC based on optical component, which has an advantage for achieving high-resolution operation at fast sampling rate., also it consume less power. We investigate the performance of the proposed ADC theoretically. The analysis results show that this proposed ADC is promising to obtain ENOB of greater than 8 bit at the sampling rate of 8 GS/s. REFERENCES [1] Yong Liu, Qianshu Zhang Wavelength Sampling and Quantizing Optical ADC Based on Long-period Waveguide Grating Filter IEEE proc [2] Walt Kester, Editor, Data Conversion Handbook, Published by Newnes, an imprint of Elsevier, 2005, ISBN: See in particular Chapter 3, Data Converter Architectures. In addition to detailed discussions of the various ADC and DAC architectures themselves, the chapter also includes historical aspects. [3] Jugdutt singh high speed Analog to Digital Converter for software radio application IEEE proc [4] Chris A. menkus, ols hidri A1.8-v G sample/sec 8 bit self calibrating Folding ADC with 7.26 ENOB at Nyquist frequency IEEE proc [5] j.ming and S.H.Lewis An 8b 80 M sample/sec pipelined ADC with background calibration in IEEE ISCC dig. Tech papers feb 2000.pp [6] Sing. J. and malyaniok, R. The simulation and performance of source coupled GaAs MESFET circuit conf-proc. Modeling and simulation pp ,1993. [7] P. W. Juodawlkis, J. C. Twichell, G. E. Betts, et al. Optically sampled analog-to-digital converters, IEEE Trans.Microwave Theory Tech. 49, , [8] J. C. Twichell, J. L. Wasserman, P. W. Juodawlkis, et al. High-linearity 208-MS/s photonic analog-to-digital converter using 1-to-4 optical timedivision demultiplexers, IEEE Photonic Technol. Lett. 13, , July [9] R. C. Williamson, P. W. Juodawlkis, et al. Effects of crosstalk in demultiplexers for photonic analog-to-digital converters, J. Lightwave Technol. 19, , [10] H. Zmuda, Analog-to-digital conversion using high-speed photonic processing, Proc. SPIE 4490, 84-95, [11] H. Zmuda, M. J. Hayduk, R. J. Bussjager, et al Wavelength-based analog-to-digital conversion, Proc. SPIE 4547, ,

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