BER-optimal ADC for Serial Links

Transcription

1 BER-optimal ADC for Serial Links Speaker Name: Yingyan Lin Co-authors: Min-Sun Keel, Adam Faust, Aolin Xu, Naresh R. Shanbhag, Elyse Rosenbaum, and Andrew Singer Advisor s name: Naresh R. Shanbhag Affiliation: ECE, UIUC Yingyan Lin, UIUC, MS Contact information of the speaker: yingyan@illinois.edu Degree currently working on, and expected year of completion: PhD, 2017 Research area/interests: analog and mixed signal circuit design 1

2 Please answer the following questions Hardware has been fabricated: (yes, no) yes The chip has been tested: (yes, no) yes The chip is being fabricated but not tested yet: (tested, not yet tested) tested Simulations only: (yes, no) no Technology used: 90nm LP CMOS I will be a student at the time of the presentation next February. (yes, no) yes 2

3 Abstract (less than 150 words) ADCs in serial links employ SNDR and ENOB as a performance metric as these are standard metrics for generic ADC design. This paper studies the use of information based metrics such as bit-error-rate (BER) for ADC design in serial links. A 4GS/s BER minimizing ADC for serial links in 90nm LP CMOS is presented. By treating the ADC and the backend digital circuits as a composite detector and setting the quantization thresholds of the ADC to minimize the BER, the required ADC resolution is reduced. Measurement results show the BER achieved by the 3-bit non-uniform ADC-based receiver is lower by a factor of 10 5 and 10 7 as compared to the 4-bit uniform and 3-bit uniform ADC-based receivers, respectively, at a TX amplitude of 210 mv ppd. 3

4 Motivation & Problem Statement Motivation & background of your research - The emergence of ADC based multi-gb/s serial link receivers has enabled the application of digital signal processing techniques to recover data under severe channel impairments. A major impediment in ADCbased receiver design is the implementation of the low power and high-speed ADC. Problem statement - Explore low power ADC design for serial links 4

5 Previous work by other groups [1] showed that an adaptive minimum-ber equalizers outperform conventional MMSE equalizers over a wide variety of channels. [2] demonstrated the benefits of adapting the transmit and receive equalizer coefficients, and the sampling phase of the CDR, to minimize the BER in serial links. An ADC-based receiver was designed [3] using a low-gain analog and mixed-mode pre-equalizer in conjunction with non-uniform reference levels for the ADC. The work in [3] adjusts a pseudo-ber metric (voltage margin) to minimize BER which in effect emulates an ADC with BER-optimal reference levels. [4] proposed a power efficient equalizing receiver front-end that includes a two-step adaptation BER minimizing equalizer algorithm. These works demonstrate that the use of informationbased metrics such as the BER are indeed quite effective in reducing power of link components in serial links. 5

6 Previous Work from Your Group [5] proposed BER-optimal ADC where quantization levels and thresholds are set non-uniformly to minimize the BER. And [6] extended the work in [5] with more general theoretical analysis and simulation results. However, the results in [5] and [6] were obtained under the assumption that the ADC components were ideal, i.e., the ADC consists of a sampler with infinite bandwidth and a quantizer without metastability. Both the finite sampling bandwidth and the metastability may affect the BER. 6

7 Contribution from You Differentiate with you or your co-author s previous publications - This work studies the use of information based metrics such as BER for ADC design in serial links, and design a prototype IC to verify the benefits of the BER-optimal ADCbased receiver on silicon. If there are multiple authors*, what is YOUR contribution? - I designed the 4GS/s ADC in the prototype IC, measured the performance of the standalone ADC, and then took the major responsibility to configure the ADC chip with the backend FPGA to work as a BER-optimal ADC-based receiver. 7

8 BER BER-optimal ADC Concept bn [ ] Driver Backplane Channel noise nt () x c (t) VGA t xt () xn [ ] yn [ ] Digital ADC Equalizer w Slicer ˆ[ ] bn Conventional ADC (fidelity criterion) - Treated as a standalone component - Designed as waveform preserver BER-optimal ADC (detection criterion) - ADC + digital equalizer + slicer as a composite detector - Adjust thresholds t, according to h and w, to minimize BER - 1-bit reduction of flash ADC 50% power savings (assuming ideal ADC model) CLK CLK Recovery SNR (db) 8

9 BER-optimal ADC for Serial Links Register bank ADC chip Storage capacitor ADC_IN+/- Thermometer-to- Binary encoder Storage cap ADC core SDI SCI DAC_CLK CLK_IN+/- 8-bit DAC Comparator array Clock distribution OUT[3:0] Composite detector 4-bit 4-GS/s Flash ADC, IBM 90nm LP CMOS (1P 8M) 15 pre-amps, 3-stage metastability latches, Gray-encoder DAC controlled references, 3bit/4bit configurable ADC mode Channel BERoptimal ADC ENC QL-UD Data Sync F-block Weight update Back-end FPGA Slicer PRBS Gen. Register Bank DAC Clk Chip microphotograph 9

10 ADC ENOB [bits] Link Test Measured ADC Performance Link Test Environment BERT BERT ADC input frequency [GHz] OUT[3:0] FPGA CLK+ Board ADC FPGA board ADC PCB board CLK- ADC+ Channel ADC- SCI/SDI Stand-alone 4b ADC measurement results - Power consumption: 59.7 mw (ADC core only) - FOM = 1.42 pj/conv.-step (ADC core only) Channel Board 10

11 ADC ENOBs and Link BERs ENOB vs. input freq. BER vs. TX amplitude 3 1.E-02 ENOB[bits] 2 1 4b unif 3bunif 3b nonunif BER 1.E-04 1.E-06 1.E-08 3b unif 1.E-10 4b unif E-12 30mV 3b nonunif ppd fin[ghz] TX amplitude [mvppd] Measured ADC ENOB vs. input frequency and BER vs. TX amplitude at 4-Gb/s when ADC FSR is 100 mv ppd. ENOB is not the right metric for designing ADCs for serial links BER achieved by the 3-bit BER optimal ADC-based receiver is lower by a factor of 10 5, as compared to the 4-bit uniform ADCbased receiver. 11

12 Comparison Table ADC operating mode 3b non-uniform 4b uniform Technology 90-nm LP CMOS (1P8M) Core die area 0.38 mm 2 Supply voltage Data rate Power consumption 1.2V for analog, 1.28V for digital & clock 4 Gb/s ADC (FOM) 30.7 mw 59.7 mw B/E digital *30 mw *28 mw This work JSSCC12 [3] ISSCC09 [7] ISSCC11 [8] ISSCC08 [9] Process 90-nm LP 65-nm 65-nm 65-nm 90-nm Data Rate [Gb/s] Number of bits < < < < This work achieves the lowest BER (< ) with a 3-bit resolution and better energy efficiency than ADC-based receivers [7], [8], [9] based on comparable technologies. N/A RX power [mw] 60.7/ RX efficiency [pj/bit] * 15.2/ * * Digital back-end power estimated from synthesis in 90-nm LP CMOS 12

13 References [1] C.-C. Yeh and J. Barry, Adaptive minimum bit-error rate equalization for binary signaling, IEEE Transactions on Communication, vol. 48, no. 7, pp , Jul [2] E.-H. Chen, W. Leven, N. Warke, A. Joy, S. Hubbins, A. Amerasekera, and C.-K. Yang, Adaptation of CDR and full scale range of ADC-based SerDes receiver, in 2009 Symposium on VLSI Circuits, June 2009, pp [3] E. Chen, et al., 10 Gb/s serial I/O receiver based on variable ADC, IEEE Symp. VLSI Circuits, pp , [4] S. Son, H.-S. Kim, M.-J. Park, K. Kim, E.-H. Chen, B. Leibowitz, and J. Kim, A 2.3-mW, 5-Gb/s lowpower decision-feedback equalizer receiver front-end and its two-step, minimum bit-error-rate adaptation algorithm, IEEE Journal of Solid-State Circuits, vol. 48, no. 11, pp , Nov [5] M. Lu, N. Shanbhag, and A. Singer, BER-optimal analog-to-digital converters for communication links, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 2010, pp [6] R. Narasimha, M. Lu, N. Shanbhag, and A. Singer, Ber-optimal analogto-digital converters for communication links, IEEE Transactions on Signal Processing, vol. 60, no. 7, pp , July [7] J. Cao, et al., A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s serial links over backplane and multimode fiber, ISSCC Dig. Tech. Papers, pp ,371a, [8] B. Abiri. et al., A 5Gb/s Adaptive DFE for 2 Blind ADC-Based CDR in 65nm CMOS, ISSCC Dig. Tech. Papers, pp , [9] O. Agazzi, D. Crivelli, M. Hueda, et al., A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/s, ISSCC Dig. Tech. Papers, pp ,