A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs

Transcription

1 1 A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa Tokyo Institute of Technology, Japan

2 Outline 2 Motivation The Calibration Scheme Proposed Comparator Measurement Results Conclusions

3 Motivation (I) 3 Vin +VFS Comparator performance is important in comparator based ADCs. Comparators 2 N N bit -VFS Thermometer Binary Comparator offset Low linearity Low SNDR Comparator noise Low SNR

4 Motivation (II) 4 6bit Flash ADC 10bit SAR ADC ENOB [bit] ENOB [bit] 1bit offset (σ) = 1/4 LSB 1bit n (σ) = 1/2 LSB

5 Comparator Design Challenges 5 Offset Voltage Sensitivity Speed & Power V out P(high) V out V+ V in V in V- V offset σ +σ t d t Threshold CLK Transistor mismatch Parasitic capacitance Transistor Noise Circuit topology Transistor size

6 Outline 6 Motivation The Calibration Scheme Proposed Comparator Measurement Results Conclusions

7 Design Concept 7 Pre-amplifiers are used to reduce to offset voltage. However High DC gain (> 10x) => Difficult in deep sub-micron CMOS Wide bandwidth (> 1 GHz) => Large power consumption Offset calibration techniques are more suitable in deep sub-micron CMOS design.

8 Conventional Offset Calibration 8 [2] G. Van del Plas et al. ISSCC 2006 V offset I C L ds Advantage: Dynamic circuit, no static power. Drawbacks: Accuracy is limited by the resolution of C cal. Latch speed is slowed down.

9 Proposed Offset Calibration 9 V cm CAL V offset V out V in V in CAL CAL CAL CAL In In M c 2 I cp V out V cm V b V C M c 1 H I cp CAL Advantages: During the conversion mode, no static power. Wide compensation range. The resolution is variable by changing I cp. Drawback: Charge pump circuit must refresh C H frequently. V offset I C L ds

10 Outline 10 Motivation The Calibration Scheme Proposed Comparator Measurement Results Conclusions

11 Double-Tail Latched Comparator 11 The 2nd latch stage has to detect V Di in a very short time. CLK V DD 1.0 V out + V out - V out V out - t d :50-100ps Di+ Di- Di- Di+ CLK V DD V DD -0.1 V in - V in CLK CLK CLK [4]D. Schinkel et al. ISSCC n 2.1n 2.4n 2.7n 3.1n Time [s]

12 Proposed Comparator 12 Proposed comparator uses Di nodes voltage instead of CLK for 2nd stage latch timing. V DD V DD V out V out - Xi+ Xi- V out V out - t d :50-100ps Di+ CLK V DD V DD Di Di- Di+ CLK V in - V in + CLK n 2.1n 2.4n 2.7n 3.1n Time [s]

13 13 Proposed Comparator Advantages V DD V DD V out V out High 2nd latch G m (~2x) => less noise from 2nd latch Wide area input transistor => less offset from 2nd latch V DD V DD V in V in Unaffected by clock skew Less clock driving

14 14 Proposed Comparator with Calibration V DD V DD All transistor channel length is minimized. V out V out Each transistor channel width is optimized for fast latching. V DD V DD I CP V out V in V in V b H I CP V out

15 Comparison : Offset Voltage nm CMOS, 100 times Monte Carlo simulations. Same size transistors are used in each comparators. V offset Conventional V offset (σ) = 21.5 mv Proposed (CAL OFF) V offset (σ) = 13.5 mv Proposed (CAL ON) V offset (σ) = 1.3 mv Offset voltage 1/16

16 Comparison : Noise 16 V DD = 1.0 V, Fc = 4 GHz, Transient-Noise simulations. (Offset calibration is not cm = 0.6 V V n _ V n Vn 1/3 P V in V offset

17 Outline 17 Motivation The Calibration Scheme Proposed Comparator Measurement Results Conclusions

18 Layout 18 A prototype comparator has been realized in a 90 nm 10M1P CMOS technology with a chip area of mm mm 0.29 mm 0.12 mm 0.12 mm 64 comparators 64 with SR SR Latch latch.

19 Measurement System 19 Ramp wave, F in = 1MHz V out CLK CAL Without CAL V in - V cm V in + V offset V out With CAL Random V in - V in + V out CAL CAL

20 Measurement Results : Offset 20 V DD =1.0 V, F C = 250 MHz, N=64 V offset V offset

21 Measurement Results : Noise 21 V DD =1.0 V, Offset Calibration is not used. F C F C V cm

22 Performance Summary 22 Technology 90nm, 1poly, 10metals CMOS Active Area 120µm x 290µm (64 comparators) V offset (σ) CAL OFF/ON 13.7mV / 1.69mV Input eq. noise V n (σ) F c =600MHz, V cm =0.5V Supply Voltage 1.0V Power consumption 40 µw/ghz ( 20 fj/conv.)

23 Outline 23 Motivation The Calibration Scheme Proposed Comparator Measurement Results Conclusions

24 Conclusion 24 A low offset voltage, low noise dynamic latched comparator using a self-calibrating technique is proposed. Features The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mv at 1 sigma, while 13.7 mv is measured without calibration. A low input noise of 0.6 mv at 1 sigma, three times lower than the conventional one.

25 25 Thank you for your interest! Masaya Miyahara,