Qpix v.1: A High Speed 400-pixels Readout LSI with 10-bit 10MSps Pixel ADCs

Size: px

Start display at page:

Download "Qpix v.1: A High Speed 400-pixels Readout LSI with 10-bit 10MSps Pixel ADCs"

Elwin Joseph
5 years ago
Views:

1 Qpix v.1: A High Speed 400-pixels Readout LSI with 10-bit 10MSps Pixel ADCs Fei Li, Vu Minh Khoa, Masaya Miyahara and Akira Tokyo Institute of Technology, Japan on behalf of the QPIX Collaboration PIXEL2010 International Workshop, Switzerland, Sep. 6 10, 2010

2 Contents 1 Qpix Development in Japan Prototype Chip : Qpix v.0 Design of Qpix v.1 Preliminary Measurement Results Conclusion

3 Qpix Development in Japan Quad information / Quasi-3D / Q (Charge) information provided pixel Qpix TOF ( Drift time ) z-axis information TOT ( Signal width ) Density of electron in z direction Q : (SAR ADC ) the energy of the particle Pixel position x-y-axis information 2 Readout pixels Time E field TOF : Time of Flight Cathode TOT TOT : Time over Threshold Track Ionized electrons Current TOF Q Q : total charge

4 Contents 3 Qpix Development in Japan Prototype Chip : Qpix v.0 Design of Qpix v.1 Preliminary Measurement Results Conclusion

5 The Prototype Chip: Qpix v.0 4 Qpix v.0 was implemented to validate the basic function, having a pixel size of 140 μm x 200 μm. QPIX v.0 Chip Pixel Circuit 8 pixels MUX 8 pixels New!

= 330V, 5 Mev α-ray source) Some limitations :

6 Qpix v.0/gem Experiments Demonstrated its ability in 3-D tracking detector 5 Pads for charge collection Qpix v.0 A sample 3D track by Qpix (V GEM = 330V, 5 Mev α-ray source) Some limitations : no pixel pad readout scheme is too simple binary counter offset in amp and comparator

7 Contents 6 Qpix Development in Japan Prototype Chip : Qpix v.0 Design of Qpix v.1 Preliminary Measurement Results Conclusion

8 Qpix v.1 7 Pre_Pixel ANALOG DIGITAL R V 5-bit Offset Cal. Q0 Pixel Matrix (20x20) Pixel Pad Vcm Iin Amp Integrator Cs Vth 4-bit Offset Cal. Pixel Control Logic TOF_CK TOT_CK EOC Q12 Q13 Q0 1 Q7 Buffers for clock and control signals 20-bit Shift ister. C 0 10b SAR ADC 2 EOC Q_AD 10 ADC0 ADC4 Bias Chip Control Logic ADC9 Vcm Vrl Vrh Data Tofgate EN_IN S_P CK (20b Parallel) Linear Feedback Shift ister Full custom designed DFF Amp with offset calibration CLK Selgate Tofgate Comparator with Capacitance Calibration CK_Read W_XR Next_Pixel (FSR in bottom pixel) 10-bit SAR ADC Pixel pad

9 Charge Amplifier and Integrator 8 Both charge amplifier and integrator are realized with only one operational amplifier. PAD I in Integrator φ :ON φ :OFF I int Reset Amplifying & Integration V out_i I V V in out_i out I = int 1 = C R v s I I amp amp I in dt I in I amp Amplifier V out = 5 kω, 15 kω, 50 kω For Variable Gain V out V out_i Comp. out

10 SAR ADC 9 SAR (Successive Approximation ister) ADC is the optimal candidate for Qpix Low power (no static current) Compact (2 stage weighted capacitance DAC) Low speed (but we need only 6.7 MSps) Specification Process 0.18 μm CMOS Resolution 10 bit (ENOB : 8.4) Speed 8.3 Msps Power 460 μw Area 70 μm x 140 μm

11 Data Readout Scheme 10 Serial / parallel readout mode 240 Mbps readout speed is achievable. (limited by measurement environments) Readout time: 2.6 μs@ parallel mode / 54 μs@ serial mode 640-bit (Pixel column 19) 640-bit (Pixel column 18) 640-bit (Pixel column 17) 640-bit (Pixel column 1) 640-bit (Pixel column 0)

12 Chip Layout Designed for large area applications 11 mm. m. Percentage mm. Bump Position Bias 20-bit Shift ister IO Logic Pixel pad area is 48.9% of the total pixel area

13 Contents 12 Qpix Development in Japan Prototype Chip : Qpix v.0 Design of Qpix v.1 Preliminary Measurement Results Conclusion

14 Preliminary Electrical Experiment TOT of Pixel (0,0) TOF of Pixel (0,0) TOT [Count ] TOF [Count ] Ideal Meas Ideal Meas. ADC [LSB] Time [μs] ADC of Selected Pixels ADC(0,1) ADC(0,17) ADC(0,18) Ideal Q [pc] Time [μs] TOT and TOF : 10ns accuracy ADC codes show that the monotonicity can be kept Power consumption: μw/pixel Offset charge is caused by large paracitic capacitance in measurement system.

15 Qpix v.1/gem Experiments Two proposals are under way 14 Gas chamber Qpix chip PCB IO Pad Top View Qpix Pixel Pad Metal IO Wire Bonding connect to GND Gas chamber PCB Qpix chip Bump ball Pixel Pad IO Pad Flip Chip Bonding Top View 350 m square pad 400 m pitch Only wire bonding Protection for Qpix chip and bonding wires (materials and methods for discharge) Qpix chip is isolated from particles by PCB Difficulties during the flipchip bumping (curving surface of the PCB) Data will be available at the end of Sep.

16 Performance Summary 15 Qpix v.1 Qpix v.0 Timepix Number of Pixels 20 x 20 2 x x 256 Pixel dimensions 200 x 200 μm 2 ( Pixel pad included) 140 x 200 μm 2 (No pixel pad) 50 x 50 μm 2 Dynamic range 10 fc ~ 1.5 pc 100 fc ~ 1.0 pc 0.1 fc ~ 12 fc Preamp gain 0.43 mv/fc 0.4 mv/fc 100 mv/fc Comp. threshold 35 fc 245 fc 0.1 fc ADC LSB/MSB 1.5 fc/1.5 pc 15 fc/ 1.0 pc - Readout information TOF: 14 bits, 10 ns TOT: 8 bits, 10 ns ADC: 10 bits, 10MSps TOF: 14 bits,10 ns TOT: 8 bits, 10 ns ADC: 6 bits, 10MSps 14 bits, 10 ns (TOF or TOT or Photon counter) None Power/channel 150 μw 350 μw 6.5 μw + 7 μw Readout mode Serial/Parallel Switched parallel Serial/Parallel

17 Contents 16 Qpix Development in Japan Prototype Chip : Qpix v.0 Design of Qpix v.1 Preliminary Measurement Results Conclusion

18 Conclusion 17 Qpix aims at the future 3-D gas detectors Qpix v.0 chip demonstrated the ability for 3-D particle tracking Qpix v.1 is designed for large area applications and to increase the basic performance Qpix v.1/gem experiments are under way

19 Acknowledgments to all the contributors to the Qpix project, in particular Dr. S. Tanaka, Dr. Y. Arai, Dr. J. Haba, in KEK, A. Sugiyama, T. Azuma in Saga Univ., and Dr. K. Miuchi in Kyoto Univ.. Thank you for your interest! Li Fei, 18

A Low-Offset Latched Comparator Using Zero-Static Power Dynamic Offset Cancellation Technique

1 A Low-Offset Latched Comparator Using Zero-Static Power Dynamic Offset Cancellation Technique Masaya Miyahara and Akira Matsuzawa Tokyo Institute of Technology, Japan 2 Outline Motivation Design Concept