Development of Readout ASIC for FPCCD Vertex Detector

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1 1 Development of Readout ASIC for FPCCD Vertex Detector Tomoyuki Saito (Tohoku University) Y. Sugimoto, A. Miyamoto, Y. Takubo (KEK) H. Ikeda (JAXA), H. Sato (Shinsyu) K. Itagaki, H. Yamamoto (Tohoku) ALCPG Linear Collider Workshop of the America 21 March, Eugene, USA

2 Tomoyuki Saito (Tohoku), Oregon Univ. 2 Outline FPCCD Vertex detector Readout ASIC for FPCCD Performance of ASIC FPCCD readout test Second prototype Summary

Tomoyuki Saito (Tohoku), ALCPG11 @ Oregon Univ.

Pixel size : 5 mm 5 mm Sensitive thickness :15mm(Full-depleted) Multi-channel CCD sensor (32ch) Total

3 Tomoyuki Saito (Tohoku), Oregon Univ. FPCCD Vertex detector 3 FPCCD VTX can realize the good resolution and low pixel occupancy. Pixel size : 5 mm 5 mm Sensitive thickness :15mm(Full-depleted) Multi-channel CCD sensor (32ch) Total number of channel : pix/ch Total number of pixel ~ module It is important to establish the readout system. 128 pixel Sensor pixel ASIC 32ch output

4 Tomoyuki Saito (Tohoku), Oregon Univ. 4 Development of Readout ASIC We have to develop the multi-channel middle-speed readout ASIC with low power consumption. Challenging requirements for ASIC Readout speed > 10 MHz 1 train ~ 2650 bunch

5 5 Development of Readout ASIC We have to develop the multi-channel middle-speed readout ASIC with low power consumption. Challenging requirements for ASIC Readout speed > 10 MHz Noise level < 30 electrons Tomoyuki Saito (Tohoku), Oregon Univ.

6 6 Development of Readout ASIC We have to develop the multi-channel middle-speed readout ASIC with low power consumption. Challenging requirements for ASIC Readout speed > 10 MHz Noise level < 30 electron Power Consumption < 6 mw/ch We designed the ASIC satisfied about these requirements. Tomoyuki Saito (Tohoku), Oregon Univ.

7 Tomoyuki Saito (Tohoku), Oregon Univ. 7 Design of Readout ASIC ASIC design (1ch) Charge sharing ADC Pre-amplifier LPF CDS Input Noise suppression ADC ADC 5 MHz 2 = 10MHz Output LVDS driver

8 Tomoyuki Saito (Tohoku), Oregon Univ. 8 Design of Readout ASIC ASIC design (1ch) Charge sharing ADC Pre-amplifier LPF CDS Input Noise suppression ADC ADC 5 MHz 2 = 10MHz Output LVDS driver The parameters of Pre-amplifier and Low-pass filter (LPF) can be set along the command by PC.

9 Tomoyuki Saito (Tohoku), Oregon Univ. 9 Design of Readout ASIC ASIC design (1ch) Charge sharing ADC Pre-amplifier LPF CDS Input Noise suppression ADC ADC 5 MHz 2 = 10MHz Output LVDS driver The parameters of Pre-amplifier and Low-pass filter (LPF) can be set along the command by PC. Correlated Double Sampling (CDS) works effectively to suppress the noise on CCD.

10 Tomoyuki Saito (Tohoku), Oregon Univ. 10 Design of Readout ASIC ASIC design (1ch) Charge sharing ADC Pre-amplifier LPF CDS Input Noise suppression ADC ADC 5 MHz 2 = 10MHz Output LVDS driver The parameters of Pre-amplifier and Low-pass filter (LPF) can be set along the command by PC. Correlated Double Sampling (CDS) works effectively to suppress the noise on CCD. Charge sharing ADC has low power consumption.

11 Charge sharing ADC 11 Charge sharing ADC:Low power consumption A/D conversion by the charge operation between capacitance array V QP C sp cp(0) V ref V ref C sn V QM Capacitance corresponding to bit-weight cn(0) 2 N-1 C u 2 N-2 C u Tomoyuki Saito (Tohoku), Oregon Univ. Comparator

12 Charge sharing ADC 12 Charge sharing ADC:Low power consumption A/D conversion by the charge operation between capacitance array 1 Input signal is accumulated at C sp and C sn, and the comparator compares V QP and V QM. decision on the highest-bit V QP C sp cp(0) V ref V ref C sn V QM Capacitance corresponding to bit weight cn(0) 2 N-1 C 2 N-2 u C u Tomoyuki Saito (Tohoku), Oregon Univ. Comparator

13 Charge sharing ADC 13 Charge sharing ADC:Low power consumption A/D conversion by the charge operation between capacitance array 1 Input signal is accumulated at C sp and C sn, and the comparator compares V QP and V QM. decision on the highest-bit 2 Switch cp or cn (depend on the result of 1) is connected. compare V QP and V QM decision on second-bit V QP C sp cp(0) V ref V ref C sn V QM Capacitance corresponding to bit weight cn(0) 2 N-1 C u 2 N-2 C u Tomoyuki Saito (Tohoku), Oregon Univ. Comparator

ASIC readout system 14 Output (7bit) FPGA Output (Ethernet by 100 Mbps SiTCP) ASIC Working Signal Component Readout board Setting signal GNV-250 (VME) Setting signal Board for ASIC Readout board

14 ASIC readout system 14 Output (7bit) FPGA Output (Ethernet by 100 Mbps SiTCP) ASIC Working Signal Component Readout board Setting signal GNV-250 (VME) Setting signal Board for ASIC Readout board (equipped for the main FPGA) Clock production, Sending the working signal GNV-250 (VME) Setting of the parameter (Gain, LPF) PC Software process (DAQ-Middleware) The performance of ASIC was tested by the developed system. Tomoyuki Saito (Tohoku), Oregon Univ.

15 Tomoyuki Saito (Tohoku), Oregon Univ. Performance test of 1st prototype ASIC 15 The results on the performance test are summarized. Result Goal Status Readout speed 1.5 MHz 10 MHz Noise level 40 e 30 e Lack of current to ADC at high speed readout Effect on the stray capacitances 1ADC count=40e too big Some ADC counts are missing Power consumption 13 mw/ch (Simulation) 6 mw/ch Analog and digital parts are same

ADC count Tomoyuki Saito (Tohoku), ALCPG11 @ Oregon Univ. Performance test of 1st prototype ASIC 16 Linearity The results measurement on the performance test are summarized.

16 ADC count Tomoyuki Saito (Tohoku), Oregon Univ. Performance test of 1st prototype ASIC 16 Linearity The results measurement on the performance test are summarized. Result Goal Status Readout speed 1.5 MHz 10 MHz Lack of current to ADC at high speed readout Effect on the stray capacitances Noise level 40 e 30 e 1ADC count=40e too big Some ADC counts are missing Power consumption 13 mw/ch (Simulation) Input voltage (mv) 6 mw/ch Analog and digital parts are same

17 Tomoyuki Saito (Tohoku), Oregon Univ. Performance test of 1st prototype ASIC 17 The results on the performance test are summarized. Result Goal Status Readout speed 1.5 MHz 10 MHz Lack of current to ADC at high speed readout Effect on the stray capacitances Noise level 40 e 30 e 1ADC count=40e too big Some ADC counts are missing Power consumption 13 mw/ch (Simulation) 6 mw/ch Analog and digital parts are same We have to address these issues in next prototype of ASIC.

18 FPCCD readout Tomoyuki Saito (Tohoku), Oregon Univ.

19 Tomoyuki Saito (Tohoku), Oregon Univ. 19 FPCCD readout system The readout test of FPCCD was performed by the developed system. Output (7bit) Output (Ethernet by 100Mbps SiTCP) ASIC Readout board Working Signal Setting signal GNV-250 (VME) Setting signal FPCCD prototype (by Hamamatsu) Pixel size : 12 mm 12 mm Number of channel : 4

20 Tomoyuki Saito (Tohoku), Oregon Univ. 20 FPCCD readout test The signal which was sent from FPCCD to the PC is investigates. Pedestal distribution (ADC count) Uniform distribution

distribution Photomask LED irradiation test

21 Tomoyuki Saito (Tohoku), Oregon Univ. 21 FPCCD readout test The signal which was sent from FPCCD to the PC is investigates. Pedestal distribution (ADC count) Uniform distribution Photomask LED irradiation test Success in reading ILC The developed readout system works normally.

22 Tomoyuki Saito (Tohoku), Oregon Univ. Readout noise on total system 22 The pedestals on each pixels are checked to estimate the total noise (Requirement : 50e). Pedestal on pixel 5 Room temperature ADC count Measured pixel (CCD1ch)

23 Readout noise on total system 23 The pedestals on each pixels are checked to estimate the total noise (Requirement : 50e). Pedestal on pixel 5 Room Measured pixel (CCD1ch) 128 temperature ADC count Noise on each pixel (electron) Pixel Ave. Room temperature The noises at -40 equal to that of only ASIC. are satisfied with the requirement (50 electrons). Tomoyuki Saito (Tohoku), Oregon Univ. 512

24 Tomoyuki Saito (Tohoku), Oregon Univ. 24 Development of 2nd prototype ASIC Problems on the 1st prototype ASIC 1 Slow readout speed 2 Big jumps on ADC count output by the stray capacitances 3 Large power consumption

25 Tomoyuki Saito (Tohoku), Oregon Univ. Development of 2nd prototype ASIC 25 Goal : 10 MHz readout speed and solution to ADC count jumps

26 Tomoyuki Saito (Tohoku), Oregon Univ. Development of 2nd prototype ASIC 26 Goal : 10 MHz readout speed and solution to ADC count jumps Main modification Readout speed : The number of pins is increased,

27 Tomoyuki Saito (Tohoku), Oregon Univ. Development of 2nd prototype ASIC 27 Goal : 10 MHz readout speed and solution to ADC count jumps Main modification Readout speed : The number of pins is increased, Some jumps of ADC counts Addition the offset adjustment circuit to the comparator.

28 Development of 2nd prototype ASIC 28 Goal : 10 MHz readout speed and solution to ADC count jumps Main modification Readout speed : The number of pins is increased, Some jumps of ADC counts Addition the offset adjustment circuit to the comparator. Change of the ADC design for the suppression of the effect on the stray capacitance Switch Measures against the stray capacitances Comparator Tomoyuki Saito (Tohoku), Oregon Univ. Bit- weight capacitance The capacitance is divided and the bases are connected to the earth.

29 ADC count Tomoyuki Saito (Tohoku), Oregon Univ. Performance test by Post layout simulation The layout is designed by Digian Technology. Performance test by the post layout simulation (simulation by the data from layout) Linearity measurement (10MHz) 29 Input voltage(mv)

30 ADC count ADC count Performance test by Post layout simulation The layout is designed by Digian Technology. Performance test by the post layout simulation (simulation by the data from layout) Linearity measurement (10MHz) No stray capacitance 30 Input voltage(mv) Input voltage(mv) Some ADC counts are still missing because of the stray capacitance in the comparator. Tomoyuki Saito (Tohoku), Oregon Univ.

31 Tomoyuki Saito (Tohoku), Oregon Univ. Development of 2nd ASIC 2 31 More modification ADC count jump : Change on the design of the comparator Suppress the effect on the stray capacitance New comparator circuit in ADC Offset adjustment circuit Input + - Output Total design is changed to the symmetry one

32 ADC count Performance test 2 by Post layout simulation 32 The layout added more changes was also designed by Digian Technology. Performance test by the post layout simulation Layout Linearity measurement (10MHz) 1ADC count ~7 electron Input voltage(mv) The design of the second ASIC works normally at 10 MHz The 2nd prototype ASIC arrived at the end of Feb. Tomoyuki Saito (Tohoku), Oregon Univ.

Process:0.35mm CMOS Number of channel:8 Chip area size:4.3 mm 4.

33 Tomoyuki Saito (Tohoku), Oregon Univ. 33 2nd prototype of ASIC 2nd prototype ASIC Produced by TSMC Process:0.35mm CMOS Number of channel:8 Chip area size:4.3 mm 4.3 mm Test board for 2nd prototype FPCCD socket 2nd prototype ASIC packaged ASIC socket

34 Parameter setting The behaviors of the shift registers for setting the parameter (gain, filter, offset) are investigated. Behavior of the shift register in the case that 101010.

34 34 Parameter setting The behaviors of the shift registers for setting the parameter (gain, filter, offset) are investigated. Behavior of the shift register in the case that is written Clock Status value on shift register The output corresponds with the command. The parameter is set correctly by order of the PC. Tomoyuki Saito (Tohoku), Oregon Univ.

Second prototype of ASIC can be satisfied with the requirements on the readout speed and noise level in the post layout

35 Tomoyuki Saito (Tohoku), Oregon Univ. Summary and Plan 35 The 2nd prototype was developed to solve the problems on 1st ASIC. Second prototype of ASIC can be satisfied with the requirements on the readout speed and noise level in the post layout simulation. Power consumption [Simulation] : 27 mw/ch (requirement: 6 mw/ch) We received at the end of Feb. and has been tested the performance. Parameter set OK ADC check. Readout test with 6 mm 6 mm FPCCD Thickness 50 mm

36 Back up

37 ASIC 37 Input Output

38 Correlated Double Sampling (CDS) The noise can be suppressed by sampling the difference between the reset and signal level

39 Measures against stray capacitance in switch switch Stray capacitance Suppress the effect on the stray capacitance By tuning the M value which is corresponded to bit-weighted

40 40 1st prototype of ASIC 1st prototype ASIC Layout by Digian technology Produced by TSMC Process:0.35mm CMOS Number of channel:8 Size:2.85 mm 2.85 mm ASIC Layout Packaged ASIC 1ch Tomoyuki Saito (Tohoku), ILC detector yearly workshop

41 Number of A/D conversion Performance check ~Readout speed~ 41 The readout speed was checked by the pedestal distributions Pedestal distribution (ADC count) 1.5 MHz 10 MHz (requested) OK A/D conversion is abnormal. ADC count In case of 10MHz : Short of current to the comparator Stray capacitance Upper limit on readout speed ~ 1.5 MHz From now on, readout speed = 1.5 MHz Tomoyuki Saito (Tohoku), ILC detector yearly workshop

42 Number of conversions Noise level (electron) Performance check ~Readout noise~ The readout noise is estimated by the pedestal distribution. Pedestal distribution at room temperature Dependence of noise on the temperature 42 RMS = 1.0 ~40 電子 ADC count Temperature ( ) Noise level = 40 electron (Requirement:30 electron) 1ADC count = 40 electron Bad resolution to estimate the noise Small dependence on temperature (Cryostat : -50 ) Tomoyuki Saito (Tohoku), ILC detector yearly workshop

43 ADC count 43 Performance check ~Linearity~ The source of the big jumps on the output was examined by simulation. Simulation The ratio of the capacitance-array in the ADC is changed. corresponding to bit ADC count and input voltage Data - Simulation 2 N-1 C u + α 1 2 N-2 C u + α 2 The simulation agrees with the data. Input voltage (V) Source of the big jumps on the output = Stray capacitance in ADC Tomoyuki Saito (Tohoku), ILC detector yearly workshop

Tomoyuki Saito (Tohoku Univ.) Outline

1 Development of Readout system for FPCCD Vertex Detector Tomoyuki Saito (Tohoku Univ.) H. Ikeda A, K. Itagaki, A. Miyamoto B, Y. Takubo, Y. Sugimoto B, H. Yamamoto Outline FPCCD Vertex Detector Readout