Wolfgang Lohmann, BTU and DESY

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FCAL Status Wolfgang Lohmann, BTU and DESY FCAL is a R&D venture to develop novel detector technologies to instrument the very forward region of future collider ILC, CLIC are collider planned after

1 FCAL Status Wolfgang Lohmann, BTU and DESY FCAL is a R&D venture to develop novel detector technologies to instrument the very forward region of future collider ILC, CLIC are collider planned after LHC Our glue is a common physics interest Estimates of performance benchmarks are based on the Standard Model, may be changed by LHC results Labs involved: Argonne, Vinca Inst, Belgrade, Bukharest IFIN, CERN, Univ. of Colorado, Cracow UST, Cracow INP, JINR Dubna, Royal Holloway, NCPHEP Minsk, Santa Cruz, Stanford University, SLAC Tuhoku Univ., Tel Aviv, Univ., DESY (Z.)

2 Conclusion for R&D LHC is running very successfully discoveries are around the corner We should be prepared for the expected (relatively easy) but also for the unexpected (not so easy) We must be prepared with the best possible, but flexible concepts We should not be blind for innovative solutions To match this effort in R&D is mandatory R&D may be enhanced by new ideas! 2

Very Forward Instrumentation- Example ILD BeamCal

optimize detector design for precise luminosity

low polar angles), assisting beam tuning (fast

radiation hardness (BeamCal), high precision

harder challenges are expexted at CLIC Our effort

3 Very Forward Instrumentation- Example ILD BeamCal + Pair Monitor LumiCal Ongoing simulations to optimize detector design for precise luminosity measurement, hermeticity (electron detection at low polar angles), assisting beam tuning (fast feedback of BeamCal data to machine) Challenges: radiation hardness (BeamCal), high precision (LumiCal) and fast readout (both) Similar or harder challenges are expexted at CLIC Our effort so far Develop Technological Solutions to tackle the Challenges 3

4 Publications and Conference Contributions Olga, Konrad, me gave talks in the ALCPG meeting Eugene Marek on the meeting on power pulsing Wojtek at the ILD workshop in Paris Jonathan will give a talk on TIPP (practice talk here) Ivanka send an abstract to EPS conference Olga send an abstract to TWEPP are there more? If not, we should enhance our presence 4

35 μm AMS), FE ASIC and ADC FPGA as data concentrator under way FE ASIC from

5 FE ASICs Frontend readout prototype chips developed at UST Cracow, manufactured in a MPW run (0.35 μm AMS), FE ASIC and ADC FPGA as data concentrator under way FE ASIC from Stanfor/SLAC, TSMC 0.18um, 1.8V prototypes successfully tested next steps must be defined (Angel has to finish the thesis) new development for CLIC to be discussed here 5

These results and the ones from the expected testbeam in July 2011 will be our main contribution to the

6 auxiliary electronics System Beam Test in August 2010 Sensor box on the x-y mover FE ASICs Sensor Testbeam line 22 at DESY II Results to be presented here! These results and the ones from the expected testbeam in July 2011 will be our main contribution to the DBD Testbeam was performed by students! K. Afanaciev S. Kollowa J. Aguilar S. Kulis M. Chrząszcz I. Levy A. Ignatenko O. Novgorodova supervision of S. Schuwalow 6

Pad and sensor homogeneity Impact of edges.

7 Results for DBD A few million of trigger are on disk to quantify the full system Signal-to-Noise Charge collection efficiency Cross talk Pad and sensor homogeneity Impact of edges.. Will need effort for the next few months to fully understand the system and possibly publish 7

8 Next Testbeam Test of fully assembled Prototype Sectors Sensors and ASICs (+ ADC) connection (Cracow, DESY, help from other labs ) DAQ (+Tel Aviv) Preparation of the beam test in July 2011 To be discussed in detail: who will coordinate Who will participate Which components are ready for beam What we have to delay, but still to be done for the next beam 8

Pair Monitor ASIC SiO 2 sensor Pixel size: 400 x 400 μm 2 Radius:

allows the elimination of the bump-bonding process.

digital readout (preamp, discriminator, counter) manufactured chip

9 Pair Monitor ASIC SiO 2 sensor Pixel size: 400 x 400 μm 2 Radius: 10 cm Total number of pixels: ~200,000 Monolithic construction allows the elimination of the bump-bonding process. First step: design of a readout prototype ASIC for 3x3 pixels: digital readout (preamp, discriminator, counter) manufactured chip (CMOS 0.2 μm, SOI technology) performance measurements done 1 px Publication submitted! 9

10 Simulation Studies to Refine the Design BeamCal: Electron Detection Capability SB2009 beam parameter, no anti DID?? LumiCal: Physics background studies (two photon and related) at 1-3 TeV Both: - exercise of a calibration concept, using muons and Bhabhas - impact on the physics program CLIC CDR in 2011!! Contribution to be finalised here 10

midterm: Midterm Goals FP7 application (AIDA) Infrastructure to allow Physics studies after 2012 Cracow (2x), DESY, Tel Aviv, CERN + VINCA and IFIN-HH (associates) Infrastructure to tackle the

11 midterm: Midterm Goals FP7 application (AIDA) Infrastructure to allow Physics studies after 2012 Cracow (2x), DESY, Tel Aviv, CERN + VINCA and IFIN-HH (associates) Infrastructure to tackle the scientific goal: FCAL Specific infrastructure: Flexible, high precision tungsten structure Fast FE Readout Innovative connectivity scheme Module construction and test devices (jigs, mechanics and electronics test facilities) Position control devices Infrastructure common with others: Power pulsing Data acquisition Tracking in front of the calorimeter 11

CALICE AHCAL overview

International Workshop on the High Energy Circular Electron-Positron Collider in 2018 CALICE AHCAL overview Yong Liu (IHEP), on behalf of the CALICE collaboration Nov. 13, 2018 CALICE-AHCAL Progress, CEPC