ATLAS LAr Electronics Optimization and Studies of High-Granularity Forward Calorimetry

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1 ATLAS LAr Electronics Optimization and Studies of High-Granularity Forward Calorimetry A. Straessner on behalf of the ATLAS LAr Calorimeter Group FSP 103 ATLAS ECFA High Luminosity LHC Experiments Workshop October 3-6, 2016

2 Overview Upgrade of the ATLAS LAr Calorimeters LAr Forward Calorimetry at High Luminosity Legacy vs. High Granularity Performance Risks LAr Readout Electronics for High Luminosity Layout Components Developments Summary and Outlook 2

Overview The ATLAS LAr calorimeter system: electromagnetic and hadronic calorimetry up to η <4.9 182.

3 Overview The ATLAS LAr calorimeter system: electromagnetic and hadronic calorimetry up to η < readout channels design optimized for 10 years of operation at nominal LHC luminosity cm -2 s -1 3

4 Overview Three main improvements under study and development for HL-LHC: replacement of readout electronics (with exception of HEC cold pre-amplifiers) high-granularity timing detector in endcap region high-granularity forward calorimeter LAr readout electronics Motivation for upgrade: radiation tolerance improved trigger capabilities improved pile-up reduction LAr/absorber technology itself is radiation tolerant High Granularity Timing Detector High granularity LAr forward calorimeter 4

5 Overview Three main improvements under study and development for HL-LHC: replacement of readout electronics (with exception of HEC cold pre-amplifiers) high-granularity timing detector in endcap region high-granularity forward calorimeter LAr readout electronics Motivation for upgrade: radiation tolerance improved trigger capabilities improved pile-up reduction LAr/absorber technology itself is radiation tolerant High Granularity Timing Detector Dirk Zerwas Thursday at 13h00 High granularity LAr forward calorimeter 5

ATLAS Forward Calorimetry Today FCal coverage: 3.2 < η < 4.

tungsten absorber 396/508 µm LAr gaps 500+254 channels Electric

1 kv/mm HV applied using 1 MΩ and 2 MΩ protection resistors

6 ATLAS Forward Calorimetry Today FCal coverage: 3.2 < η < 4.9 FCal1 Cu absorber matrix 269 µm LAr gaps 1008 channels FCal2/3 tungsten absorber 396/508 µm LAr gaps channels Electric field across LAr gap approx. 1 kv/mm HV applied using 1 MΩ and 2 MΩ protection resistors Signals ganged in groups of 4/6/9 in FCal 1/2/3 Summing boards further combine these signals to readout channels 6

7 Simulated Single Jet in FCal1 7

Physics with Forward Jets Vector boson scattering and vector boson fusion processes at 14 TeV: requires high forward jet tagging efficiency at low pile-up jet background Missing transverse energy:

8 Physics with Forward Jets Vector boson scattering and vector boson fusion processes at 14 TeV: requires high forward jet tagging efficiency at low pile-up jet background Missing transverse energy: signature of New Physics with weakly interacting particles reduce pile-up contribution in forward region Standard Model physics forward jet production event shapes forward electron reconstruction 125 GeV 1 TeV gluon fusion if Higgs-like resonance couples as strongly as a SM Higgs: Forward calorimetry coverage is important for HL-LHC physics VBF 8

ionization rate relative to critical value: FCal at High Luminosities At HL-LHC we will have 200 collisions/crossing: 28 TeV energy deposited in FCal1 per crossing 110 W heat produced in each FCal1

9 ionization rate relative to critical value: FCal at High Luminosities At HL-LHC we will have 200 collisions/crossing: 28 TeV energy deposited in FCal1 per crossing 110 W heat produced in each FCal1 LAr boiling is avoided if T LAr reduced by ~1.6 K -- was a big concern for operating the FCal at HL-LHC Further consequences: space charge effects distort electric field and lead to pulse degradation at high η in FCal1 large ionization current leads to HV drop across LAr gap further increase of space charge effect ionization fluctuations introduce uncertainties space charge regime simulated pulse shapes at η = 4.73 normal operating regime 9

10 A High-Granularity sfcal High-granularity sfcal: smaller LAr gaps: approx 100 µm for FCal1 proven to work in HiLum testbeam no summing of channel groups in FCal1 x4 higher granularity in FCal1 at 3.2 < η < 4.3 improved pile-up suppression in particular in combination with ITk tracker extension to high η FCal 100 µm NIM A 669 (2012) 47 simulated single jet in FCal1 simulated single jet in sfcal1 10

11 Performance of High-Granularity sfcal at HL-LHC Primary effect of higher granularity: less pile-up noise per calorimeter cell More constituents for jet reconstruction with higher significance Useful ingredient for improved E T miss reconstruction 11

12 Jet-area based pile-up subtraction: regional average median p T density used to correct jet p T Projected Impact on Physics Likelihood analysis reduces number of pile-up jets per event keeping a high efficiency for hard-scatter jets for sfcal compared to FCal Variables based on calorimeter information only: jet width/mass, number density, constituent p T sum relative to jet axis 12

13 Projected Impact on Physics Forward tracking (ITk) combined with sfcal further reduces pile-up fakes of jets: assignment of pile-up and hard-scattering tracks: fewer tracks per cluster for sfcal than for FCal improved cluster-vertex-fraction x 1.7 Applied to high-mass VBF Higgs production (m "H" =1.8,2.6 TeV, narrow width): factor 1.7 better rejection of pile-up jets at 90% efficiency for hard-scattering jets above p T =20 GeV main improvement of sfcal in low p T range GeV lower jet p T threshold possible 13

Risks and Conclusion Installation of sfcal requires opening of endcap cryostat detailed engineering studies have been performed routing of signal and HV cables including +2052 additional readout

14 Risks and Conclusion Installation of sfcal requires opening of endcap cryostat detailed engineering studies have been performed routing of signal and HV cables including additional readout channels of each sfcal1 careful analysis of radiation environment The following installation risks are considered most serious, although probability of occurance might be low: debris falling in between EMEC/HEC electrodes shorts, dead channels electrical contact between electrodes and absorber during warm-up damage of fragile mechanical parts under thermal stress (warm-up/cool-down) Consequences: risk of replacement of the FCal outweighs the physics gain of an sfcal FCal will stay functional even though the detector calibration will become challenging since Ar bubble formation in FCal can be avoided: no further plan for a MiniFCal in front of the FCal 14

15 Upgrade of LAr Calorimeter Electronics LAr readout system requires upgrade for HL-LHC because: current analog pipeline on front-end is not compatible with x4 longer L0 trigger latency of 10 μs front-end and back-end systems are limited to 100 khz readout - much less than foreseen L0 accept rate of 1-4 MHz radiation tolerance requirements increase by factor 3 Front-end on detector Back-end off detector DAQ Trigger 15

16 Upgrade of LAr Calorimeter Electronics LAr readout system requires upgrade for HL-LHC because: current analog pipeline on front-end is not compatible with x4 longer L0 trigger latency of 10 μs front-end and back-end systems are limited to 100 khz readout - much less than foreseen L0 accept rate of 1-4 MHz radiation tolerance requirements increase by factor 3 Front-end on detector Back-end off detector DAQ Phase-I upgrade (LS2, 2019/20): super-cell readout readout x10 better granularity to first hardware trigger level than today 40 MHz input to future L0 trigger Trigger 16

17 Upgrade of LAr Calorimeter Electronics LAr readout system requires upgrade for HL-LHC because: current analog pipeline on front-end is not compatible with x4 longer L0 trigger latency of 10 μs front-end and back-end systems are limited to 100 khz readout - much less than foreseen L0 accept rate of 1-4 MHz radiation tolerance requirements increase by factor 3 Phase-II upgrade (LS3, ): free-running 40 MHz readout of all LAr calorimeter cells input to higher trigger levels/daq off-detector long-latency data buffering Front-end on detector Back-end off detector DAQ Phase-I upgrade (LS2, 2019/20): super-cell readout readout x10 better granularity to first hardware trigger level than today 40 MHz input to future L0 trigger Trigger 17

Front-end System ASIC development of pre-amplifier, shaping, digitization and serializer Devices may be integrated into a single Front-End System On Chip if realized in same technology direct

18 Front-end System ASIC development of pre-amplifier, shaping, digitization and serializer Devices may be integrated into a single Front-End System On Chip if realized in same technology direct interfaces, reduced power consumption, simplified cooling system (air sufficient?) Phase-II Front-End Boards (FEB2) are planned to receive clock and control signals individually no controller board necessary in front-end crate Improved calibration system is foreseen with single ASIC for pulser, DAC and digital logic 18

19 Front-end Design Main design parameters are very similar to original front-end design Re-optimisation shall take expected pile-up and experience with current system into account Dynamic range: bit LSB energy may be chosen higher than today but still sufficient for in-situ noise measurement Saturation of input signal shall be avoided expected signal currents from high p T physics (Z' ee, jets) below 10 ma in middle layer of barrel and endcap Preamplifier requirements: 2 ma / 19

20 Shaping, Gains and ADC Today bi-polar signal shaping is applied avoids baseline shift, but negative lobe ~1/6 of full amplitude range pedestal typically at 1000 counts for 12-bit ADC Unipolar shaping under investigation simulated baseline shift only about 1/10 of negative lobe for same bit precision an ADC could cover a larger amplitude range impact on powering stability and noise need to be studied (again) EM barrel 2nd layer 3 gain ranges implemented in current system: transition between medium and high gain at ~25 GeV impacts energy calibration, e.g. for Higgs mass measurement in H γγ channel aim for optimized gain ranges: 2 gain + 14-bit ADC baseline 20

21 Preamp design in 130 nm CMOS New line terminating preamp with dual range output and electronically cooled resistor Super common base amplifier (low Zin) Low noise voltage sensitive amplifier Noise: 2-gain output and easy adaptation to cable impedance 21

130 nm CMOS Preamp Impedance flat over wide frequency range: variation below 1Ω for 10 khz to 100 MHz Integral non-linearity <0.2% for CR-RC 2 shaping Low noise: 150 na with 1.

22 130 nm CMOS Preamp Impedance flat over wide frequency range: variation below 1Ω for 10 khz to 100 MHz Integral non-linearity <0.2% for CR-RC 2 shaping Low noise: 150 na with 1.5 nf Low power: 15 mw LAUROC0 chip layout completed and prototype submitted in April with various settings (Z in, R f ) Results from testboard measurements expected soon preamp characterization irradiation tests in more complete setup with calibration input, shaper, ADC Design planned to migrate to 65 nm at a later stage 22

steps (3 bits) ENI ~57nA rms at 260 pf, Linearity within 0.1% at 9 ma, 0.

23 Fully differential amplifier with passive feedback Very stable termination (R and N independent of signal current) Noiseless capacitive feedback sets gain dual range, programmable termination and gain, trimmable impedance +/- 3% steps (3 bits) ENI ~57nA rms at 260 pf, Linearity within 0.1% at 9 ma, 0.5% at 10 ma 65 nm CMOS Preamp Power: 100 mw/ch from single 1.2V supply Layout design is being finalized, Chip is about to be submitted Frequency (Hz) 23

ADC Development Quad 12-bit ADC in 130 nm for super-cell readout exists (Phase-I): 4 bit pipeline + 8 bit SAR 43 mw/channel Phase-II design started in 65 nm (TSMC): 8 lane 14 bit exploit 12-bit SAR

24 ADC Development Quad 12-bit ADC in 130 nm for super-cell readout exists (Phase-I): 4 bit pipeline + 8 bit SAR 43 mw/channel Phase-II design started in 65 nm (TSMC): 8 lane 14 bit exploit 12-bit SAR with calibration unit and Dynamic Range Enhancer (DRE) output is serialized at 320(640) MHz: 5.12 Gb/s total connects to lpgbt (9 Gb/s) Test chip with DRE submitted Yearly test chip submissions start in spring '17 aiming for full prototype in 2020 analog references power cuts digital ADC channels initial layout power cuts 24

25 Commercial ADCs Evaluation of commercial ADCs - selection of promising chips according to power and costs 20 candidates for 14-bit ADC 7 candidates for 16-bit ADC Different vendors, different sampling rates Irradiation tests are planned to be done in the coming months Phase II Status 25

lpvlad (low-power version) 4-channel 10 Gb/s VCSEL driver arrays in 65 nm receive low-swing CML - compatible with lpgbt

26 Optical Link Baseline is lpgbt in 65 nm CMOS: mux, encoder, serializer could be integrated with FE and ADC into a single chip Development of laser array drivers and optical transmitter modules within VL+ project: VCSEL Array Driver VLAD and lpvlad (low-power version) 4-channel 10 Gb/s VCSEL driver arrays in 65 nm receive low-swing CML - compatible with lpgbt output lpvlad: 35 ps jitter 22 mw/channel output ma measured eye diagram lpvlad at 10 Gb/s in multichannel mode 26

with lpvlad/vlad further reduce height to 4.

27 Optical Transmitter ATx (Array optical Transmitter): 12-channel optical transmitter Mechanical optical interface from US Connect, AZ8 connector from Samtec Tested together with lpvlad/vlad further reduce height to 4.5 mm Commercial VCSEL+transmitter arrays are also explored as alternative: a 4-channel device has been tested successfully at 10 Gb/s 27

Powering Main DCDC converter from a few hundred V to 48 V/24 V/12 V if

FEB2 boards Based on Si power MOSFET Redundancy implemented in current

radiation tolerance Next step: investigate GaN transistors Successful

28 Powering Main DCDC converter from a few hundred V to 48 V/24 V/12 V if possible in accessible detector area further down-conversion directly on FEB2 boards Based on Si power MOSFET Redundancy implemented in current converter design Commercial components also promising, except for gamma radiation tolerance Next step: investigate GaN transistors Successful irradiation tests with "power off", more tests on different development boards planned Phase II Status 28

LAr Backend Electronics at HL-LHC LAr back-end performs digital processing of digitized waveforms calculation of energy in each LAr cell reduction of electronics and pile-up noise in each cell

29 LAr Backend Electronics at HL-LHC LAr back-end performs digital processing of digitized waveforms calculation of energy in each LAr cell reduction of electronics and pile-up noise in each cell area-based pile-up subtraction long-latency buffering of data until L0 accept (1-4 MHz) resp. L1 accept A fraction of the full cell read-out can be sent to L0Calo at 40 MHz on low-latency data path, e.g. to improve granularity of FCal trigger information Concentration of information of Δη x Δφ = 0.2 x 0.2 area requires high performance FPGA processing power and 120 or more I/O fibers Fiber remapping plant connects front-end to back-end 29

LAr Backend Electronics Basic design of back-end pre-processor is planned to be similar to Phase-1 LATOME + LArC boards: ATCA main board with mezzanine processor cards LATOME with Arria 10 FPGA Data

30 LAr Backend Electronics Basic design of back-end pre-processor is planned to be similar to Phase-1 LATOME + LArC boards: ATCA main board with mezzanine processor cards LATOME with Arria 10 FPGA Data are received and sent on optical fibers: 10 Gb/s from lpgbt at input maximum achievable speed at output (~30 Gb/s) Evaluation of modern FPGA models (Xilinx Ultrascale, Altera Stratix 10 etc.) has not yet started but will profit from experience with LATOME design and experience by ATLAS TDAQ group 30

Readout Optimisation Using Simulation Front-end foresees programmable features, but some design choices need to be made Simulation framework for Phase-II electronics: fully simulated collision events

31 Readout Optimisation Using Simulation Front-end foresees programmable features, but some design choices need to be made Simulation framework for Phase-II electronics: fully simulated collision events with pile-up up to µ=200 and configurable LHC bunch pattern realistic electronics noise description is being improved realistic digital data processing: ADC bit precision, sampling rates 40 MHz and 80 MHz, realistic FPGA operations etc. Ongoing work: study of different readout schemes: bipolar/unipolar shaping, sampling rate, dynamic range, gain, linearity, digital signal processing,... conversion from noise power spectrum to noise time series Example: extended optimal filter with feedback loop at 80 MHz for pile-up correction 31

32 Summary and Outlook High-granularity sfcal studied in great detail ATLAS will continue to run with FCal due to installation risks LAr calorimeter electronics are being optimized for highest luminosities: provide high/full granularity input to new ATLAS trigger radiation-tolerant electronics components for free-running mode are being developed final design choices require more simulations: interplay between analog and digital readout parameters Goal is best LAr calorimeter performance at HL-LHC 32

33 More Information 33

34 More Information CERN-LHCC

The Compact Muon Solenoid Experiment. Conference Report. Mailing address: CMS CERN, CH-1211 GENEVA 23, Switzerland

Available on CMS information server CMS CR -2017/349 The Compact Muon Solenoid Experiment Conference Report Mailing address: CMS CERN, CH-1211 GENEVA 23, Switzerland 09 October 2017 (v4, 10 October 2017)