Motivation Overview Grounding & Shielding L1 Trigger System Diagrams Front-End Electronics Modules

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1 F.J. Barbosa, Jlab Motivation Overview Grounding & Shielding L1 Trigger System Diagrams Front-End Electronics Modules Safety Summary 1

2 1. Motivation Hall D will begin operations with a photon flux of 107/s Level 1 Trigger rate will range from 108/s later. 20 khz to 200 Need Pipelined Front-End Electronics How? A simplified Level 1 Trigger & DAQ Model: Trigger Every Event Analog Input Front-End Digitizer Pipeline FE/DAQ Interface Every n Events Event Block Buffers To ROC 2

3 2. Overview - Hall D in Perspective Downstream North South Upstream 3

4 Hall D Electronics Rack Locations FCAL FDC CDC Cable Routing TOF ST BCAL 4

5 3. Grounding & Shielding - Site Civil Construction Plans for Hall D Have Been Completed Low Impedance Grounding Grid Below Floor Slab 5

6 Grounding & Shielding - Hall Low Impedance Bonding to Grounding Grid Equipment Segregation for Low Noise Each Detector is Referenced Separately to Ground Shields Do Not Carry Return Currents Hall D Guidelines Management & Safety 6

7 4. L1 Trigger VXS Infrastructure We have extensive VME expertise at Jlab (VME64x ANSI/VITA 1.5): VME64x + High-Speed Switched Serial Fabric = VXS (ANSI/VITA 41.0) Energy Sum Trigger Clock & Signal Distribution Low Jitter Lab Tests: Crate Trigger Processor fadc250 ROC 20-slot VXS Crate 8 fadc250 8 fadc250 Trigger Interface Module Crate Trigger Processor Signal Distribution Module 7

8 Frontend Electronics Requirements for the L1 Trigger Photon Tagger Start TOF Counter BCAL BCAL Inner Outer Type Scintillator Scint. Scint. Sci Fiber Sci Fiber Lead Glass Channel Count Signal Source 144 PMT 120 SiPM PMT PMT SiPM PMT PMT w/cw Discrimination 144 LE 120 CFD CFD CFD LE - - fadc bit, F1TDC 60 ps 60ps 60 ps 60 ps - - Level 1 Trigger Hit Bits Hit Bits Hit Bits Energy Sum Energy Sum Energy Sum Detector FCAL CUSTOM 250 MSPS 8

9 fadc250 A simplified view of the VXS flash ADC Timing & Control Data Processing & VME CH 16 P1 Signal Conditioning & ADC Virtex 4 LX25 EP2S30 VME Path Stratix II CH 9 Data, Configuration Virtex 4 CH 8 P0 FX20 VXS-P0 Path MEM LX25 P2 CH 1 VME Data & Control MEM Data Processing & VXS Serial Data, Timing, Control P2 Path Data, Timing, Control VXS Trigger, Clock & Signal VME Data & Control 9

10 fadc250 Sampling, Readout & Trigger 4 ns r Sample Trigger Threshold 0 Trigger Latency Trigger Window Hit Bits Trigger - Energy Sum to P0 - Sum samples from all 16-channels, every 4 ns. - Hit Bits to P0 - Hit pattern word from all 16-channels, every 4 ns. Data Readout through VME Samples or sum within the trigger window. Trigger Latency and Trigger Window are user programmable. 10

11 fadc MSPS Pipelined flash ADC Developed and Tested for 10- and 12-bit Applications Good Linearity & Resolution (ENOB = 10 & bits) 16 channels - No Cross-talk User Selectable Input Ranges (-0.5V, -1V, -2V) Pipelined, 8 µs Latency, Windowing Energy Sum, Hit Bits Output via VXS for L1 Trigger VXS Serial Interface (6.25 Gbps aggregate rate) VME64x 2eSST (VME320 / VITA ) Presented at the IEEE NSS 2007 Five Units Under Test. Cost per Module - $3,348* * Prices subject to change without notice. 11

12 ( ) Number in parentheses refer to number of modules Trigger Latency ~ 3 μs Detector Signals (16) (1) (1) Fiber Optic Links Clock/Trigger 62.5MHz (1) (12) (1) (1) Fiber Optic Link (~100 m) 125 MHz) fadc250 (8) CTP Crate Trigger Processor (2) (1) SD Signal Distribution Copper Ribbon Cable (~1.5 m) 250 MHz) TI Trigger Interface VXS Backplane 12

13 Trigger Modules and Their Functions A Summary TS (Trigger Supervisor) - Validates Triggers (from 32 Inputs) and Issues Trigger Word. - Master Clock (250 MHz). - Synchronization Control. TD (Trigger Distribution) - Fanout (Trigger Word/Clock/Sync). - Handles Status/Busy Signals from TI Modules. TI (Trigger Interface) - Issues Fixed Latency Trigger (3 bits) to all Front-end Modules (based on Trigger Word from TD and through SD modules). - Handles Status/Busy Signals from Front-end to TD Modules. - Clock Distribution to SD Module (250, 125 & MHz). SD (Signal Distribution) - Distributes De-skewed Clock, Trigger & Sync to all Front-end Modules or Trigger Word to TD Modules. - Handles Status/Busy Signals from Front-end to TI Module. CTP (Crate Trigger Processor) - Collects and Processes Energy Sum & Hit Bits from 16 Front-end Modules and Adds Time Stamp One Crate. - Output to SSP Module. SSP (Sub-System Processor) - Collects and Processes Energy Sum & Hit Bits from up to 8 CTP. - Sub-System Skew Adjustment. - Output to 2 GTP Modules. GTP (Sub-System Processor) - Collects and Processes Energy Sum & Hit Bits from 8 SSP. - SD Functions (Clock, Trigger & Sync distribution). - Computes Trigger Algorithm (32 bits): -Energy Sum (Bcal & Fcal) -Track Count (TOF, ST) - Max/Min Hits (Tagger). - Output 32-bit Trigger 4 ns to TS Module. 13

14 Clock & Signal Distribution: Because of ADC speed (250 MSPS) and resolution (12-bit), we need a low jitter clock signal distribution implementation. Use commercially available hardware Tested 150 m Multi-Mode Fiber Bundle with <2 ps Jitter 14

15 Clock, Trigger Word & Sync (CLKSYNC) Globally Distributed Over Optical Fibers. CLK250 is not encoded (CW signal). CLKSYNC 4-bit serial encoded command with fixed latency. Trigger Word 16-bit serial encoded (SerDes) and DC balanced (Aurora protocol) Transmitter: Fixed Latency Receiver: Delay Adjustments 15

16 5. System Diagrams Electronics Summary Detectors in Hall D not Involved in the L1 Trigger Detector Pair Spectrometer CDC FDC Type Scintillator Drift Drift Channel Count Anodes Cathodes Signal Source PMT Anode Wire Anodes Cathode Strips Discrimination LE No Anodes: Yes (ASIC) fadc bit, 125 MSPS No Yes Cathodes: Yes F1TDC 60 ps No Anodes: 115 ps 16

17 17

18 18

19 6. Front-End Electronics for the Drift Chambers Preamp Ionizing Track +HV Pipelined DAQ Cathode Strips R FDC fadc C Disc TDC fadc Anode Wire For the cathode strips, q+ ~ 1/5 q- R CDC Straw Tube C fadc HV Ionizing Track Anode Wire GND 19

20 The GlueX ASIC Prototype GAS-1 8-Channel Preamp Designed by UPenn (M. Newcomer, et al) in collaboration with IUCF and JLab. Fabricated (Summer 2007) by TSMC in 0.25 μm CMOS, submitted through MOSIS. Photograph of GAS-1 ~ 4 mm Block Diagram of the GlueX ASIC Prototype: Wire-bonds (Au) 8 Channels 11 ns peaking time GAS-1 Die Linearity - 0.8% to 300 fc (0.25 μm CMOS) Lead-frame (QFN 64 9x9 mm) < 0.05% Cross-talk 3000 e- ENC@ 20 pf 20

21 1500 mv 24-ch Preamp Card & Signal Cable Excellent results < 1% cross-talk Low noise Good Linearity Low Power. Design & Layout of GAS-2 almost complete. Cost ~ $150/card 21

22 ASIC & Preamp Card Ongoing Developments GAS-2 Improvements (Design & Process): - Noise - Dynamic Range - Gain Linearity New: - Gain Selection - Discriminator Design & Layout Completion April 2008 New Sections Submission 2008 Tests with CDC and FDC Prototypes are Ongoing: (Preamp, 18 m Cable, fadc125 Shaper Prototype) - Evaluate S/N - Determine Gain, Dynamic Range - Optimize Shaping for fadc125 Thermal Performance Tests with Cooling System Prototype. 22

23 INPUT VME FIFO MEZZANINE SIGNAL CONDITIONING INPUT 72 channels (3 groups of 24) GlueX Preamp Card test pulser output 450 mv differential input range, >66 db common-mode rejection over ±3 V common-mode range Cable response equalization (peak gain 1.6) 5th order shaper anti-alias filter, 24 ns peaking time 125 MSPS, 12 bit resolution (14 bit assembly option) Pipelined, 13 µs buffer, 200 khz trigger rate FPGA-based digital signal processing (e.g., extract time & pulse integral) 1 MByte output data FIFO VME64x 2eSST, VXS (clk & trig in) Construction: 6U main board & mezzanine 36 channels each Estimated cost per module - $4,053 INPUT 7. Modules - fadc MSPS Pipelined flash ADC CLK & TRIG INPUT DATA FPGA ADC 23

24 F1TDC High Resolution Pipelined TDC F1TDC Thermal Profile Presented at the IEEE NSS 2002 About 100 Modules in Use at Jlab Cost per Module - $3,422* * Prices subject to change without notice. 24

25 Commercial Modules Available Today - Although Hall D is a few years away from construction, some commercial modules and systems are already available today. A1535N HV Module ($6,710)* V895 Discriminator ($3,791)* * Prices subject to change without notice. SY1527 HV Chassis [CAENET, Ethernet, RS-232] ($8,190 LC Version)* LV Modules (MPV Series) ($2,523)* MPOD EV LV Chassis [CANbus, Ethernet, USB] ($5,509)* 25

26 Modules & Units in Hall D 26

27 8. Safety Safety is a major consideration in developing the Hall D instrumentation: High Voltage Distribution Systems - Fully Interlocked - Programmable V & I Trips - Minimize HV Channels Wherever Possible SiPMs Require Low Voltage (30 V) CW Voltage Multipliers Require Low Voltage (24 V) - HV Cables are Shielded and Grounded Low Voltage Distribution Systems - Fully Interlocked - Programmable V & I Trips - Segmentation for Lower Power Distribution Grounding & Shielding Systems - Comprehensive plan with reference at detector front-end - Floating LV & HV supplies minimizing ground loops - Minimizing supply & return loop areas - Separated from magnet supplies, quenching loads, pumps, etc. 27

28 9. Summary We have made considerable progress in prototyping the front-end electronics: - ASIC - Preamp Card - Receiver Shaper (Part of fadc125) - fadc250 - F1TDC - Crate Trigger Processor Module - Low Jitter Signal Distribution. We have established comprehensive plans for: - HV, LV and grounding distribution - Electronics systems and Installation. We are addressing safety considerations from design inception and towards a comprehensive and integrated safety plan. 28

29 Backup 29

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