SAM (Swift Analogue Memory): a new GHz sampling ASIC for the HESS-II Front-End Electronics.

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Agnes Pitts
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1 SAM (Swift Analogue Memory): a new GHz sampling ASIC for the HESS-II Front-End Electronics. E. Delagnes 1, Y. Degerli 1, P. Goret 1, P. Nayman 2, F. Toussenel 2, P. Vincent 2 1 DAPNIA, CEA/Saclay 2 IN2P3/LPNHE Jussieu 1

Working since 2002 Principle of the stereoscopy The night Imaging Cherenkov Technic

2 Principle of the Hess 1 Experiment Very High Energy (100GeV-10 TeV) Gamma Ray observatory. Composed of 4 telescopes (100m 2 mirror, 15 m focal). Working since 2002 Principle of the stereoscopy The night Imaging Cherenkov Technic The night The ground Image of source is somewere along image of shower axis... Use more views to locate source! 2

=> Sophisticated Very fast digitizing electronics

3 The Hess 1 Camera Very compact. Located at the focal point of the telescopes. Modular design 960 PMs in 60 drawers. Very small exposure time (<16ns) to reduce the noise. => Sophisticated Very fast digitizing electronics integrated in the camera. Integration of a HESS 1 camera at LPNHE Photon detectors and electronics 3

4 The HESS 1 Front-end Electronics. ARS0 Fanout signal entry 12 bits ADC Multiplexor Readout channels Connection to photo-tubes 8 x comparators Adder Buffers Fpga output local trigger Digital Analogue Amplifications Enable/disable (4 channels) Trigger channels 4

5 The ARS0 chip. Gsample/s sampling Chip originally developed for the ANTARES experiment. Based sampling-dll technique : One SCA memory cell 5 channels /chip, 128 cells per channel. 1 GHz Readout ~ 1 MHz/sample Low power (500mW) The ARS0 chip (AMS 0.8µm techno) 5

6 Principle of the Analogue Ring Sampler The signal is continuously sampled in the ARS. When a trigger occurs in a sector, the sampling is stopped and all the ARS are read. Trigger => end of sampling The read-operation starts from the last written cell - a programmable offset (trigger latency+ ). The number of cells to read (Nf) is programmable. On the FE board, two read-out modes are available: sample = all the Nf cells are read. charge = The Nf cells are summed 6

Increase of Night Sky Background (NSB) Increase of count rate (up to 50kHz).

7 From HESS to HESS2 At least one more big telescope (S=600m 2,F=35m, 2000 PM). Decrease the threshold at 10 TeV. But : Increase of dynamic range (1to 3000 SPE). Increase of Night Sky Background (NSB) Increase of count rate (up to 50kHz). => Need for a new FE electronics Sensitivity 10 mc 100 mc 1 C Single large Phase II telesc. 4 additional telescopes HESS phase I Energy 1 GeV 10 GeV 100 GeV 1 TeV 10 TeV 100 TeV 7

8 The Hess2 new Front-End electronics. Hess 1 FEE dead Time= 275 µs limited by the ARS readout time. Hess2 architecture main improvements: Faster analogue Sampler => SAM: same functionalities as in ARS0, but improved characteristics. 1 ADC/channel L2 buffer. 8

9 The SAM chip vs ARS0 chip specifications. ARS0 SAM justification channels/chips 5 2 (1 low gain,1 high gain) Crosstalk, modularity. Number of Cells Trigger 1 latency. Sampling Frequency 1 GS/s 1 to 2 GS/s Dead-time/ precision trade-off Read-out time for 20 cells 60µs <2 µs Dead Time (expected rate =50kHz) Bandwidth 80MHz >300MHz Integration window decrease = noise and NSB effect decrease Dynamic range 9 bits 12 bits Physic dynamic range Cross-talk? 0.1% High and Low gain mixing Power consumption 500mW <500mW Cooling, compactness Technology CMOS AMS0.8µm CMOS AMS0.35µm Technology obsolescence Not compatible with a linear sampling structure: => use a matrix structure. 9

The SAMPLING MATRIX structure The Memory cells are arranged in a matrix and not on a line Principle already proven in the MATACQ chips of the 2GSample/S,12 bit MATACQ VME boards.

10 The SAMPLING MATRIX structure The Memory cells are arranged in a matrix and not on a line Principle already proven in the MATACQ chips of the 2GSample/S,12 bit MATACQ VME boards. Very High Dynamic Range and High Sampling Rate VME Digitizing Boards for Physics Experiments, E. Delagnes et al, accepted for publication in IEEE Transaction on Nuclear Sciences (2005). Advantages Bandwidth/power ratio Fast Parallel read operation. Square Chip geometry. => Lower noise. Drawbacks - One pedestal/line - Read pointer position system. 10

11 SAM: global architecture Other key features: Analog input Write Buffers Readout Control Sampling Control + Stop Synchronisation Write i Read col i 256 =16x16 memory cells Sampling Frequency servo control rst Readout Sequencer and analog serializer Readout amplifiers ANALOG MUX ADC SAM_rck SAM_read Analog output Digital output Convert programmable test points. Special readout modes (programmable starting cell). Pedestal equalization. Auto setup at power on. Needs very few command lines to operate. SAM_din SAM_rck SAM_sc Serial Link SAM_dout DAC for pedestals equalization Not in SAM0. Option for SAM1 11

12 SAM: How to find the position of the first cell to read MATRIX of Internal MATRIX SAMpling TDC inside the sampling Matrix cells WP Y 16 bits XY (16 LSbits) encoder LWC (4 LSbits) X 16 bits XY (16 MSbits) encoder ND (4 LSbits) ND (4 MSbits) adder carry SAMPLING MATRIX decoder LWC (4 MSbits) decoder adder FCR (4 MSbits) FCR (4 LSbits) 12

13 The SAM0 Prototype 2 differential channels*256 cells Techno AMS CMOS 0.35 µm. Size ~11 mm2 ~60k transitors. QFP100 (0.5mm pitch) package 16mmx16mm footprint Submitted 6/12/04. Under tests at Jussieu on a prototype of a HESS2 front-end board since April. Acquisition with ADC is working since Friday june 17th 13

5-3 GSample/s. Readout Time : 1.6µs / 16 cells (fck= 11MHz can probably be doubled).

14 SAM0: results All tested functionalities are ok and in specs. No abnormal Jitter Power Consumption : ~ 300 mw. Maximum Sampling Freq : GSample/s. Readout Time : 1.6µs / 16 cells (fck= 11MHz can probably be doubled). Analog Bandwidth : 250 MHz-300MHz. 400mV 4.5ns Input 400mV 5.5 samples Output Readout ck = 11MHz: 16 cells read in 1.6µs 14

15 SAM: results Operation at 400kHz is ok: => Fast DLL servo is ok. 2.5µs Total channel Noise < 0.8mV rms (measured on the x30 high gain channel with a non-optimized set-up) = 26µV at input of the chain. Before pedestal equalization: σ = 2.5mV rms After on-chip line pedestal equalization: σ = 0.8mV rms Max signal >2V => Dynamic range > 11.3 bits 15

16 SAM: results with electrically simulated PMT signal An electrically simulated SPE is clearly out of the noise. baseline 1SPE 3.3SPE Integration over a 16 cell-window (not optimum for noise). Crosstalk < 0.1% Linearity still to be characterized 16

SAM0 seems usable for HESS 2 without any modifications.

17 Conclusions, Future Plans Up to know, the SAM0 chip is fully working. Need more characterization (especially concerning linearity). SAM0 seems usable for HESS 2 without any modifications. New SAM1, including an ADC, will be prototyped next September. Production (of SAM0 or SAM1 depending on the results) will be launched at the beginning of 2006). 17

PoS(PhotoDet 2012)030

PoS(PhotoDet 2012)030 NECTAR: New Electronics for the Cherenkov Telescope Array a, J. Bolmont a, P. Corona a, E. Delagnes b, D. Dzahini c, F. Feinstein d, D. Gascon e, J.-F. Glicenstein b, P. Nayman a, F. Rarbi c, M. Ribó e,