SPADIC Status and plans

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Kerry Hoover
5 years ago
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1 SPADIC Status and plans Michael Krieger TRD Strategy Meeting Michael Krieger SPADIC Status and plans 1

2 Reminder: SPADIC 1.0 architecture from detector pads single message stream: signal snapshot + metadata LVDS serial link channel channel channel. channel MUX CBMnet analog digital CSA ADC DSP Hit Logic 32 Michael Krieger SPADIC Status and plans 2

3 Charge sensitive amplifier + preamplifier pole-zero shaper 440 µm input range: 75 fc h(t) t e t/τ shaping time: τ = 80 ns two amplifiers per channel selectable: positive polarity (4 5 mw) negative polarity (10 mw, not optimized) layout & schematics: modular, scalable Michael Krieger SPADIC Status and plans 3

4 CSA characterization simulation + previous testchips: ENC = pf (300 0 pf) tuning of bias settings local noise minimum ENC = q S/N(q) = q σ h(q) q? = 1.8V 15(?)fF S/N 180 (CSA + ADC) Michael Krieger SPADIC Status and plans 4

5 CSA pulse shapes Michael Krieger SPADIC Status and plans 5

6 CSA jump increase R FB CSA jumps away from op. point recover: turn amplifier off/on luckily away from good settings Michael Krieger SPADIC Status and plans 6

7 ADC 8 pipelined stages input current 2 doubled residual current using current storage cell comparator result: 1, 0, +1 DAC current mode pipelined design 25 MHz sample rate, continuously running 9 bit nominal output (2 s complement) resolution 8 bits 4.8 mw, rad-hard layout, µm 2 Michael Krieger SPADIC Status and plans 7

8 ADC measurements INL + noise: taken at 20 MHz sample rate, preliminary bias settings +2 LSB red: purple: mean value ±1σ 2 LSB limit of dynamic range Michael Krieger SPADIC Status and plans 8

Digital signal processing 9 16 16 9 multiply-add scaling & offset with saturation logic IIR filter with 4 first order stages 16 bit internal resolution 6 bit

9 Digital signal processing multiply-add scaling & offset with saturation logic IIR filter with 4 first order stages 16 bit internal resolution 6 bit coefficients freely programmable ( ,...,+ 32 ) 0 8 average quantization error [LSBs] Bits Michael Krieger SPADIC Status and plans 9

10 Digital signal processing purpose: ion tail cancellation shorten pulses reduce pileup/help hit logic tail added using modified input tail removed with IIR filter normal pulse shape (from δ input pulse) effect on double pulses Michael Krieger SPADIC Status and plans 10

11 Hit logic ADC/DSP neighbor trigger global trigger hit detector dual threshold optional differential mode timestamp, channel number, trigger type, etc. continuous stream of 9 bit samples (25 MHz) metadata generator data wrapper 9 15 bit format 32 bit selection mask content of message words identified by preamble message builder 16 bit output format snapshot of signal at trigger time (up to 32 samples according to mask) Michael Krieger SPADIC Status and plans 11

12 Selection mask examples mask message data (hex) A 801F 9082 AEEF 5AFF 3FDF 73E E 0F77 47E2 B samples contained B 801F 9E4D AF0F 52FF 3FCA 404F 4200 B1D0 7 samples contained allows tradeoff between quality of signal reconstruction and data volume Michael Krieger SPADIC Status and plans 12

13 Message size (selection mask) n words = nsamples n samples = 0 also works!, 1 n samples 32 offset: 3 words (channel/group ID, timestamp, hit type, stop type) Michael Krieger SPADIC Status and plans 13

14 Multi hits What happens when a channel is triggered again, before the current message is completed? first message would end here new trigger first message is gracefully aborted selection mask is restarted (in this example, all bits are selected...) +24 timestamp: 3031 data (24 values): -30,..., -35 hit type: self triggered stop type: multi hit timestamp: 3055 data (32 values): -31,..., -32 hit type: self triggered stop type: normal end of message Michael Krieger SPADIC Status and plans 14

15 Message output multiplexing ordering FIFO channel numbers one-hot encoded 17 channel 0 channel 1... channel output buffers channel 15 epoch ch inserts epoch markers MUX merged message stream 0 sorted by timestamp! 2 (group A, B) Michael Krieger SPADIC Status and plans 15

16 Error handling What happens when a channel output buffer is full? Test case: input signal: square wave, period = 30 time bins (>600 khz hit rate) reconstructed output signal: no problem with only one channel active force buffer overflow with neighbor trigger MUX can t read fast enough timestamp: 3525 data (30 values):... hit type: self triggered stop type: multi hit timestamp: 3555 data (20 values):... timestamp: 3615 hit type: self triggered buffer overflow count: 2 special info message stop type: channel buffer full Similarly for ordering FIFO, incl. handling of flipped bits (SEU). Michael Krieger SPADIC Status and plans 16

17 CBMnet interface SPADIC CBMnet clk generator ref. clk error checking, retransmission start/stop, sync, trigger 4 DLM 4 LVDS deterministic latency messages (DLM) register file 16 ctrl maps data + control traffic to serial LVDS links ch. group A 16 data 500 Mbit/s (DDR), 8b/10b encoded (1 input, ch. group B 16 data 2 outputs) Michael Krieger SPADIC Status and plans 17

18 Plans Current test setup rev. A voltage regulators detector test pulse injection Michael Krieger status LEDs CBMnet (HDMI) SPADIC Status and plans power FPGA board Susibo USB 18

19 Plans Packaging: QFP176 (23 mm) Michael Krieger SPADIC Status and plans 19

20 decoupling etc. Power SPADIC SPADIC SPADIC Plans New PCB rev. B3x Harwin Harwin Harwin HDMI HDMI HDMI 3 packaged SPADICs on PCB distance: 114 mm (matching TRD layout) PCB size 15 cm 40 cm Michael Krieger SPADIC Status and plans 20

21 Plans SPADIC wish list some obvious fixes (serializer glitch, CBMnet retransmission, comparator,... ) increased input range (75 fc 200 fc) drop/reduce functionality (IIR filter,... ) needs user experience and/or specification CBMnet 3.0 (W. Müller, DAQ Meeting Nov. 21) should leave SPADIC logic untouched (or I didn t fully understand) needs proper specification! Michael Krieger SPADIC Status and plans 21

22 Spadic Self triggered Pulse Amplification and Digitization asic Michael Krieger SPADIC Status and plans 22

Multi-Channel Charge Pulse Amplification, Digitization and Processing ASIC for Detector Applications

1.0 Multi-Channel Charge Pulse Amplification, Digitization and Processing ASIC for Detector Applications Peter Fischer for Tim Armbruster, Michael Krieger and Ivan Peric Heidelberg University Motivation