D16G. 16 Channel Programmable Delay. Features. General Description. Block Diagram. Top View CMU-PNPI

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1 6 Channel Programmable Delay General Description The is a custom designed 6-channel programmable delay circuit. Each channel coists of an input LVDS-to-CMOS level converter; four stages of delay with, 2, 4, and 8 steps; and output width pulse shaper. Also, the chip has the possibility to generate a test level at each output. This option is used for testing chip-to-chip connectio. The chip has a serial interface to control the delay and set the output test level. The is designed and fabricated using a CMOS.5 micron technology. The chip is capsulated into a QFP-64L X plastic package. This ASIC is designed as a part of the anode front-end electronics for Cathode Strip Chambers of the Endcap of the Muon System of CMS experiment. Top View Features Input signal level Input resistance Output signal Number of delay steps 5 Delay step (slope) Output pulse width Power supply voltage Power coumption Temperature drift Block Diagram Id LVDS standard Ohm 3.3 V CMOS - 4 (adjustable with an external current) 4 (adjustable with an external current) 3.3 V.2 W.6 / o C Iw LVDS LVDS /TTL /TTL Delay Delay Pulse Pulse width width MUX MUX 6 SEL (63) 33 CHSB (8) CLK (9) DIN (2) CLRB (62) Delay Control T,,T4 Test Level C, C6 DOUT (6) 7 Size: mm x mm x mm. Pin pitch:.5 mm.

2 6 Channel Programmable Delay Pin Configuration Out Out2 Out3 Out4 Out5 Out6 Out7 Out8 Out9 Out Out Out2 Out3 Out4 Out5 Out6 Gnd CHSB CLK DIN Id Gnd In6_N In6_P In5_N In5_P In4_N In4_P In3_N In3_P Gnd SEL CLRB DOUT Iw Gnd In_P In_N In2_P In2_N In3_P In3_N In4_P In4_N Pin In5_P In5_N In6_P In6_N In7_P In7_N In8_P In8_N In9_P In9_N In_P In_N In_P In_N In2_P In2_N

3 6 Channel Programmable Delay Electrical Characteristics PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input signal level LVDS standard Input impedance Rinp Ohm Output signal 3.3 V CMOS Minimum delay Tdel.min Pin Id connected to Gnd via K, delay code Delay step (slope) Sd Adjustable with an external current 4 /LSB Number of delay steps 5 Delay nonlinearity Sd/2 Channel-to-channel difference within chip dt Sd Output pulse width Tpulse Pin Iw connected to Gnd via 2K. 4 Output pulse rise time Load capacitance 5 pf 4 Output pulse fall time Load capacitance 5 pf 4 Output current Iout 5 ma Power supply voltage 3.3 V Power coumption P.2 W 3

4 6 Channel Programmable Delay Test Performance Number of the chips Delay, A B Delay Code Delay chip distribution vs. delay at code 5. Typical samples of delay vs. delay code. A group 7, delay slope 2.2 /LSB B group, delay slope.5 /LSB Chips Chips (groupe 7) Maximum Integral Nonlinearity, 4

5 6 Channel Programmable Delay Temperature dependence 27 Average Delay (code ), Temperature, o C Delay vs. temperature (code ). Delay vs. temperature (code 5). Average Slope, /LBS Temperature range 36 º C - 85 º C Delay drift rate -.6 / º C * ** *) Maximum delay residual for code **) Maximum delay residual for code 5 Delay slope and residual vs. temperature. 5

6 6 Channel Programmable Delay Delay Slope Tuning by Voltage Test circuit in out 5 V k Id Vd k Vd Control voltage Id Control current Delay code = cotant Delay code 5 =.42 / mv Slope (Va) =. / mv Control Voltage, mv Delay slope vs. Control Voltage. Control Voltage, mv Minimum delay (delay code ) vs. Control Voltage. Control Voltage, mv Maximum delay (delay code 5) vs. Control Voltage. 6

7 6 Channel Programmable Delay Delay Slope Tuning by Current Control Current, ua Delay code = cotant Delay code 5 = -.93 / µa Slope (Ia) = -.3 / µa Delay slope vs. Control Current. Control Current, ua Minimum delay (delay code ) vs. Control Current. Control Current, ua Maximum delay (delay code 5) vs. Control Current. 7

8 6 Channel Programmable Delay Single-Channel Structure Multiplexer logic table. E A B Out X X X X 8

9 6 Channel Programmable Delay Control Logic C, C2,, C6 test level bits T, T2, T3, T4 delay control 9