DEI1160 PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INPUT INTERFACE IC. Device Engineering Incorporated FEATURES PIN ASSIGNMENTS

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1 Device Engineering Incorporated 35 East Alamo Drive Chandler, AZ 55 Phone: (40) Fax: (40) DEI0 PROGRAMMABLE GND/OPN & /OPN DISCRETE INPUT INTERFACE IC FEATURES Eight discrete inputs o Individually configurable to see either GND/OPEN or /OPEN(or /GND) discrete signals o Hysteresis provides noise immunity o ma input current to prevent dry relay contacts. o Internal isolation diode o Inputs protected from Lightning Induced Traients per DO0E, Section, Cat A3 and B3. o Inputs protected from Power Input Abnormal Surge per DO0E, Section, Cat Z. Serial I/O interface to read data register and write configuration register o Direct interface to Serial Peripheral Interface (SPI) port. o TTL/CMOS compatible inputs and Tristate output o 0MHz Data Rate o Serial input to expand Shift Register Logic Supply oltage (CC): 3.3 or 5 Analog Supply oltage (DD): 5 +/-0% L SOIC EP package PIN ASSIGNMENTS DIN DIN DIN3 DIN4 DIN5 DIN DIN7 DIN DEI0 DD GND CC SEL SCLK Figure DEI0 Pin Assignment ( Lead SOIC) 03 Device Engineering Inc. of 3 DS-MW-00-0 Rev D

2 FUNCTIONAL DESCRIPTION The DEI0 is an eight-channel discrete-to-digital interface IC implemented in an H DMOS technology. It sees eight discrete signals of the type commonly found in avionic systems and converts them to serial logic data. Each input can be individually configured as either GND/OPEN or /OPEN format input via a serial data input command. The discrete data is read from the device via an eight-bit serial shift register with 3-state output. This serial interface is compatible with the industry standard Serial Peripheral Interface (SPI) bus. Table Pin Descriptio PINS NAME DESCRIPTION - Discrete Inputs. Eight discrete signals which can be individually configured as either GND/OPEN or /OPEN format inputs. 9 Logic Output. Serial Data Output. This pin is the output from MSB (Bit ) of the selected shift register (Data/Configuration). It is clocked by the rising edge of SCLK. This is a 3-state output enabled by. 0 SCLK Logic Input. Serial Shift Clock. A low-to-high traition on this input shifts data on the serial data input into Bit 0 of the selected shift register. The selected shift register is shifted from Bit 0 to Bit 7. Bit 7 of the selected shift register is driven on DOUT. Logic Input. Chip Select. A low level on this input enables the 3- state output and the selected shift register. A high level on this input forces DOUT to the high impedance state and disables the shift registers so SCLK traitio have no effect. When the Data register is selected, a high-to-low traition causes the Discrete Input data to be loaded into the Data register. When the Configuration Register is selected, a low-to-high traition causes the Serial Configuration register data to be loaded into the parallel configuration outputs. Logic Input. Serial Data Input. Data on this input is shifted into the LSB (Bit ) of the selected shift register on the rising edge of the SCLK when input is low. 3 SEL Logic Input. Selects between the Serial DATA and CONFIGURATION registers. H = DATA, L = CONF. 4 CC Logic Supply oltage. 3.3 or 5 5 GND Logic/Signal Ground DD Analog Supply oltage. +5+/-0% 03 Device Engineering Inc. of 3 DS-MW-00-0 Rev D

3 SCLK Control Logic SEL MU ENB SFT/LD SCK CONFIGURATION REG bit Shift Register w/ latched parallel output PDO[:] (D0) DD CC CFG_SEL[:] DISCRETE AFE Channels to DOUT[:] GND SFT/LD SCK PDI[:] DATA REG bit Shift Register w/ Parallel Input (D0) Figure FUNCTION DIAGRAM dd 00K DIN N 0K dpd 0 dp 0 K dpda 50 0K + os dd AMP 400khz cc + - Comparator DOUT N qna 0v REFERENCE SELECT threshold CFG_SEL N Figure 3 DISCRETE AFE FUNCTION DIAGRAM 03 Device Engineering Inc. 3 of 3 DS-MW-00-0 Rev D

4 Table Truth Table SEL SCLK DESCRIPTION H HI Z Not Selected H L alid DIN[] DR[:] H L DR[] DR[] DR[n+] DR[n], DR[] L L CR[] CR[] CR[n+] CR[n], CR[] L L HI Z CL[:] CR[:] Legend: DR = Data Register CR = Configuration Register CL = Configuration Latch Discrete AFE The Discrete Input Analog Front End circuit function is represented in Figure 3. Each DINn signal is conditioned by the resistor / diode network and presented to an amplifier followed by a comparator with hysteresis. When the input is configured for GND/OPEN operation, the pull-up resistor & diode is enabled and the appropriate amplifier offset voltage and comparator threshold voltage are selected. When configured for /OPEN, the pull-down resistor is enabled and the amp/comparator is appropriately configured. Some notable features are: The input current is ~ma. This current will prevent a dry relay contact. The input threshold voltage and hysteresis: o The falling th > 3.5. o The rising th < 4. o Hysteresis is maximum practical to meet the threshold requirements. Input noise immunity is maximized with a combination of voltage hysteresis and use of a slow input voltage comparator The inputs can withstand continuous input voltages of 40 minimum. The isolation diode breakdown voltage is greater than 45. The 0K Ohm input resistor is designed to limit diode breakdown current to safe levels during traient events. Data Register The -bit Data Register is a parallel-input, serial-output register that samples the input channels and reads-out the data to the Serial Data Output. The register is read via the output as described in Figure 4 and Figure 5. A low input level results in a Logic 0, and a high input level results in a Logic. Configuration Register The -bit Configuration Register is a serial-input, parallel-output with data latch register that individually configures each AFE input as either GND/OPEN or /OPEN format. The register is programmed via the serial data input as described in Figure and Figure 7. Logic 0 sets the respective input to /OPEN mode (pull-down); Logic sets the respective input to GND/OPEN mode (pull-up). The register is Reset to 0 s when the cc Logic Supply voltage traitio from low to hi, thus initializing the AFE inputs to a pull-down state. 03 Device Engineering Inc. 4 of 3 DS-MW-00-0 Rev D

5 Serial Interface The DEI0 incorporates a serial IO interface for programming the Discrete Input configuration and for reading the Discrete Input status. Refer to Figure. The interface is SPI compatible and coists of, SEL, SCLK,, and signals. Waveform Figures 4 7 depict the Data Read sequence and Configuration Write sequence for both -Bit cycles and also bit daisy chain applicatio. Power Up Initialization The DEI0 incorporates an on-chip power-up reset circuit and power sequencing provisio to force the DIN inputs to the /Open (internal pull down) state upon power. The reset circuit monitors the CC logic supply and forces the Configuration Register to the Logic 0 (/Open) while CC is stabilizing. The AFE circuit is designed to present the /Open (internal pull down) condition when DD supply is present and CC is below operational voltage. SEL SCLK ALID DIN DIN7 DIN DIN5 DIN4 DIN3 DIN DIN DIN inputs latched into DATA S-Reg Figure 4 Read Data Register SEL SCLK ALID SI SI7 SI SI5 SI4 SI3 SI SI DIN DIN7 DIN DIN5 DIN4 DIN3 DIN DIN SI SI7 SI SI5 SI4 SI3 SI SI DIN inputs latched into DATA S-Reg data shifted to after bit delay Figure 5 Read Data Register, Bit Daisy Chain 03 Device Engineering Inc. 5 of 3 DS-MW-00-0 Rev D

6 SEL SCLK PDO[:] Internal Config Latch Present Configuration n = New Configuration Data Bits n = Present Configuration Bits Figure Write Configuration Register New Configuration SEL SCLK PDO[:] Internal Config Latch n = Daisy Chain Data Bits n = New Configuration Data Bits n = Present Configuration Bits Present Configuration New Configuration Figure 7 Write Configuration Register, bit Daisy Chain 03 Device Engineering Inc. of 3 DS-MW-00-0 Rev D

7 LIGHTNING PROTECTION DINn inputs are designed to survive lightning induced traients as defined by RTCA DO0E, Section, Cat A3 and B3, Waveforms 3, 4, and 5A, Level 3. See waveforms below. 50% /I 5% to 75% of Largest Peak Peak T =.4us T = 70us 0 t 50% F = MHZ and 0MHZ 0 T T t Figure oltage / Current Waveform 3 Figure 9 oltage Waveform 4 Waveform Source Impedance characteristics: Waveform 3 oc/isc = 00 / 4A => 5 Ohms Waveform 4 oc/isc = 500 / 00A => 5 Ohms* Waveform 5A oc / Isc = 500 / 500A => Ohm* *Amplitude tolerances are +0%, -0%. Peak 50% /I T=40us T=0us 0 T T t Figure 0 Current/oltage Waveform 5A 03 Device Engineering Inc. 7 of 3 DS-MW-00-0 Rev D

8 ELECTRICAL DESCRIPTION Table 3 Absolute Maximum Ratings PARAMETER MIN MA UNITS cc Supply oltage dd Supply oltage -0.3 Operating Temperature Plastic Package C Storage Temperature Plastic Package C Input oltage Continuous DO0E, Waveform 3, Level 3 DO0E, Waveform 4 and 5, Level 3+ DO0E, Abnormal Surge oltage, 00ms CC +.5 CC Logic Inputs DOUT Power 5 C: (> 0 Sec) L SOIC 0.3 W Junction Temperature: Tjmax, Plastic Packages 45 C ESD per JEDEC A4-A Human Body Model Logic and Supply pi DIN pi Peak Body Temperature (0 sec duration) 35 C Notes:. Stresses above absolute maximum ratings may cause permanent damage to the device.. oltages referenced to Ground Supply oltage Logic Inputs and Outputs Table 4 Recommended Operating Conditio PARAMETER SYMBOL CONDITIONS CC DD 5.0±0%, 3.3±0% 5±0% 0 to CC Discrete Inputs 0 to 40 Operating Temperature Plastic Ta -55 to +5 ºC 03 Device Engineering Inc. of 3 DS-MW-00-0 Rev D

9 Table 5 DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS () LIMITS UNIT Logic Inputs/Outputs MIN NOM MA IH HI level input voltage CC = 5 CC = IL LO level input voltage 0. Ihst Input hysteresis voltage, SCLK input (3) 50 m OH HI level output voltage IOUT = -0uA CC 0. CC IOUT = -4mA, cc = OL LO level output voltage IOUT = 0uA 0. IOUT = 4mA, cc = I IN Input leakage in = cc or GND -0 0 ua I OZ 3-state leakage current Output in Hi Impedance state. OUT = IHmin, ILmax -0 0 ua Discrete Inputs, Configured as Ground/Open (internal pull-up) IH HI level input voltage 4 49 R IH HI level Din-to-GND resistance Resistor from Din to GND to guarantee HI input condition. 50K Ohm I IH HI level input current in =, DD = 5 in = 49, DD = ua ma IL LO level input voltage R IL LO level Din-to-GND Resistor from Din to GND to 500 Ohm resistance guarantee LO input condition. I IL LO level input current in = 0, DD = ma Ihst Input hysteresis voltage Discrete Inputs, Configured as /Open (internal pull-down) IH HI level input voltage 4 49 I IH HI level input current in =, DD = ma IL LO level input voltage I IL LO level input current in =, DD = ua Ihst Input hysteresis voltage Power Supply ICC Max quiescent logic supply in(logic) = cc or GND 3.5 ma IDD current Max quiescent analog supply current IN[:]= open in(logic) = cc or GND IN[:]= Open IN[:]= GND, All configured as Ground/Open Notes:. Ta = -55 to +5 ºC. DD = +5±0%, CC = 3.0 to 5.5 unless otherwise noted.. Current flowing into device is positive. Current flowing out of device is negative. oltages are referenced to Ground. 3. Guaranteed by design. Not production tested ma 03 Device Engineering Inc. 9 of 3 DS-MW-00-0 Rev D

10 Table AC Electrical Characteristics (4) SYMBOL PARAMETER CONDITIONS LIMITS (, 7) Min Max UNIT f MA SCLK frequency. (50% duty cycle) (5) CC = MHz t W SCLK pulse width. (5) CC = t su Setup time, SCLK low to. CC = t h Hold time, to SCLK. CC = t su Setup time, DIN valid to. us t h Hold time, to DIN not valid. 5 t su3 Setup time, N valid to SCLK. CC = t h3 Hold time, SCLK to N not valid. CC = t su4 Setup time, SEL valid to. CC = t h4 Hold time, SEL valid to. CC = t p Propagation delay, to DOUT CC = valid. () 0 t p Propagation delay, SCLK to DOUT CC = valid. () 50 t p3 Propagation delay, to DOUT HI- Z. () () (3) CC = t p4 Delay time between active. (5) CC = C in Maximum logic input pin Capacitance. 0 pf (5) C out Maximum DOUT pin capacitance, 5 pf output in HI-Z state. (5) Notes:. DOUT loaded with 50pF to GND.. DOUT loaded with K Ohms to GND for Hi output, K Ohms to CC for Low output. 3. Timing measured at 5%CC for 0 to Hi-Z, 75%CC for to Hi-Z. 4. Sample tested on lot basis. 5. Not tested. Ta = -55 to +5ºC. DD = +5, IL = 0, IH = CC unless otherwise noted. 7. Measurements made at 50%CC. 03 Device Engineering Inc. 0 of 3 DS-MW-00-0 Rev D

11 SEL tsu4 t h4 tsu th tw tp4 SCLK tsu th /fmax valid tsu3 th3 valid tp tp tp3 D/C0 D/C Figure Switching Waveforms ORDERING INFORMATION Part Number Marking Package Burn In Temperature DEI0-SES DEI0 SES EP SOIC No -55 / +5 ºC DEI0-SMS DEI0 SMS EP SOIC No -55 / +5 ºC DEI reserves the right to make changes to any products or specificatio herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose. 03 Device Engineering Inc. of 3 DS-MW-00-0 Rev D

12 APPLICATION INFORMATION The 0 power dissipation varies with channel configuration and operating conditio. Figure shows the device package power dissipation for various conditio. This includes the contributio from Supply currents and Input currents. The four curves are as follows: Table 7 Legend for Power Dissipation Curves CURE ID CONFIGURATION SUPPLY OLTAGE PROCESS ACTIE CHANNEL / TEMPERATURE CONDITION +/OPN-Nom All channels = 3.3, 5 / 7ºC Typical /OPN +/OPN-Wst All channels = 5.5,.5/ 5ºC Worst case /OPN (Low resistance and fast traistors) GND/OPN-Nom All channels = 3.3, 5 / 7ºC Typical GND GND/OPN GND/OPN-Wst All channels = GND/OPN 5.5,.5 / 5ºC Worst case (Low resistance and fast traistors) GND DEI0 Pwr Dissipation Graph Pwr Dissipation (mw) /OPN-Nom +/OPN-Wst GND/OPN-Nom GND/OPN-Wst Number CH Active Figure Power Dissipation for arious Conditio 03 Device Engineering Inc. of 3 DS-MW-00-0 Rev D

13 PACKAGE DESCRIPTION - L Narrow Body EP SOIC Moisture Seitivity: MSL / 0 C ja: ~40 C/W (Mounted on 4 layer PCB with exposed pad soldered to PCB land with thermal vias to internal GND plane) jc: ~0 C/W Lead Finish: SnPb plated Exposed Pad: Electrically Isolated from IC terminals. The PCB design and layout is a significant factor in determining thermal resistance ( ja) of the IC package. Use maximum trace width on all power and signal connectio at the IC. These traces serve as heat spreaders which improve heat flow from the IC leads. The exposed heat sink pad of the SOIC package should be soldered to a heat-spreader land pattern on the PCB. The IC exposed pad is electrically isolated, so the PCB land may be at any potential, typically GND, for the best heat sink. Maximize the PCB land size by extending it beyond the IC outline if possible. A grid of thermal IAs, which drop down and connect to the buried copper plane(s), should be placed under the heat-spreader land. A typical IA grid is mil holes on a 50mil pitch. The barrel is plated to about.0 ounce copper. Use as many IAs as space allows. IAs should be plugged to prevent voids being formed between the exposed pad and PCB heat-spreader land due to solder escaping by the capillary effect. This can be avoided by tenting the IAs with solder mask. Figure 3 Lead Narrow Body EP SOIC Outline 03 Device Engineering Inc. 3 of 3 DS-MW-00-0 Rev D