DEI1046A OCTAL ARINC 429 LINE RECEIVER

Transcription

1 Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ Phone: (480) Fax: (480) DEI1046A OCTAL ARINC 429 LINE RECEIER FEATURES Octal ARINC 429 to TTL/CMOS logic line receivers Operates from single +5 ± 10% or 3.3 ± 10% power supply ARINC inputs internally protected to lightning requirements of DO-160 Level A3 Operates in high noise environment o Input Common oltage Range: ± 20 o 2 minimum Input hysteresis Package: 38L TSSOP, 4.4 mm body DEI1046A Withstands inadvertent short to 115 ac on inputs DEI1046A PINOUT Table 1 DEI1046A Pin Description PIN NAME DESCRIPTION 15, 13, 11, 9, 7, 5, 3, 1 16, 14, 12, 10, 8, 6, 4, 2 IN[8:1]A IN[8:1]B 17 NC Not connected. 429 INPUTS. ARINC 429 format serial digital data A inputs. 429 INPUTS. ARINC 429 format serial digital data B inputs. 18 TESTA LOGIC INPUT, Test input A 19 TESTB LOGIC INPUT, Test input B 21, 23, 25, 27, 32, 34, 36, 38 20, 22, 24, 26, 31, 33, 35, 37 OUT[8:1]A OUT[8:1]B LOGIC OUTPUTS. CMOS/TTL format serial digital data A outputs. LOGIC OUTPUTS. CMOS/TTL format serial digital data B outputs. 29 DD POWER INPUT. 5 or , 30 SS POWER INPUT. Ground Device Engineering Inc. Page 1 of 8 DS-MW Rev B

2 FUNCTIONAL DESCRIPTION The DEI1046A is a BiCMOS device which contains eight differential line receivers. Each receiver channel translates incoming ARINC 429 data bus signals (tri-level RZ bipolar differential modulation) to a pair of TTL/CMOS logic outputs. Each channel operates independently and meets the requirements of the ARINC 429 Digital Information Transfer Standard. Refer to Figure 1 DEI1046A Block Diagram and Truth Table. The device is designed to operate in a high noise environment. Inputs are accepted over a +/- 20 common mode voltage range and the receivers provide over 2 olts of hysteresis. Circuit speed is optimized to reject high frequency transients. All ARINC input pins are designed with internal protection from damage due to transients meeting the lightning induced transient requirements of DO-160 Level A3. The DEI1046A device provides logic level TEST inputs for built in system test. They force the outputs of all eight receivers to the specified ZERO, ONE or NULL state. The ARINC inputs are ignored when the device is in test mode. The DEI1046A has a single test port which controls all 8 channels. The ARINC inputs incorporate on-chip lightning protection by use of high value resistors on the inputs to minimize IR heating. The resistors have dielectric isolation to withstand the voltage transients. The inputs withstand lighting induced transients up to and including DO160 Level 3 pin injection levels. Higher levels can be achieved with the addition of external TS devices between the inputs and SS, or alternately, TS devices in combination with series current limiting resistors between the ARINC bus and the IC/TS node. The series resistors reduce the power requirement and size of the TS. Resistor values up to 10K ohms are feasible. The ARINC inputs withstand inadvertent short to 115 ac aircraft power without sustaining damage. Figure 1 DEI1046A Block Diagram and Truth Table 2018 Device Engineering Inc. Page 2 of 8 DS-MW Rev B

3 ELECTRICAL DESCRIPTION Table 2: Absolute Maximum Rating PARAMETER MIN MAX UNITS Supply oltage (with respect to SS) Storage Temperature C Input oltage, continuous (ARINC Inputs) 115 ac Power 85 C 800 mw Junction Temperature, Tjmax (limited by molding compound Tg) 145 C Peak Body Temperature 260 C Lightning Protection (ARINC 429 Channel Inputs) Waveform 3 (2) Waveform 4, 5A, 5B (2) (3) ESD JS HBM 1B Class Notes: 1. Stresses above these limits can cause permanent damage. 2. Per DO160, Sect 22 Level 3A. See Figures 3, 5 and Inputs can be protected to withstand higher stress by adding series resistors and shunt TS on inputs. Inputs withstand 1500 Waveform 5A when clipped 600. Table 3: Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS Supply oltage DD +5 ±10% +3.3 ±10% Logic Input Levels TESTA,B 0 to DD Operating Temperature -TES -TMS Ta -55 to +85 C -55 to +125 C 2018 Device Engineering Inc. Page 3 of 8 DS-MW Rev B

4 Table 4: Electrical Characteristics Conditions: Temperature: -55 C to +85 C (-TES); -55 C to +125 C (-TMS) DD = +5 ±10% or 3.3 ±10% PARAMETER TEST CONDITION SYMBOL MIN MAX UNITS ARINC INPUTS A B = Logic +1 OUTA = A B = Logic -1 OUTB = A B= Logic Null OUTA = 0 OUTB = 0 NULL Input Hysteresis HY Input Common Mode oltage Range Input Resistance IN A to IN B Input Resistance IN A or IN Bto SS Input Capacitance IN A to IN B Input Capacitance IN A or IN Bto SS OUTPUT HIGH OLTAGE TTL OUTPUT LOW OLTAGE TTL OUTPUT HIGH OLTAGE CMOS OUTPUT LOW OLTAGE CMOS DDCurrent Logic +1, Null, Logic -1 CM DD open, Shorted to SS or +5 (1) DD open, Shorted to SS or +5 DD open, Shorted to SS or +5 (1) DD open, Shorted to SS or +5 (1) LOGIC OUTPUTS I OH= -5 ma (DD = 5.0 ) I OH= -5 ma (DD = 3.3 ) TTL Compatible R IN 280 kω R S 140 kω C IN 10 pf C S 10 pf OH 2.4 I OL= 5 ma (DD = 5.0 ) OL 0.4 I OH= 100 µa CMOS Compatible I OL= 100 µa CMOS Compatible SUPPLY CURRENT Data Rate = 0MHz, INA/B = open, OUTA/B = open, DD = 5.5 or 3.63 OH OL DD 50m SS+ 50m I DD ma Notes: 1. Guaranteed by design, not production tested. 2. Current flowing into device is positive. Current flowing out of device is negative. All voltages are with respect to SS unless otherwise noted Device Engineering Inc. Page 4 of 8 DS-MW Rev B

5 Table 5: Switching Characteristics PARAMETER TEST CONDITION SYMBOL INA/B to OUTA/B Prop Delay INA/B to OUTA/B Prop Delay TESTA = TESTB = 0 C L = 50 pf TESTA = TESTB = 0 C L = 50 pf MAX DD 3.3 MAX DD 5 UNITS t LH ns t HL ns OUTA/B rise time 10% to 90%, C L = 50 pf t r ns OUTA/B fall time 10% to 90%, C L = 50 pf t f ns TESTA/B to OUTA/B Prop delay TESTA/B to OUTA/B Prop delay C L = 50 pf t TOH ns C L = 50 pf t TOL ns 2018 Device Engineering Inc. Page 5 of 8 DS-MW Rev B

6 INA Largest Peak /I 25% to 75% of Largest Peak dif = 6.5 INB dif = 2.5 t HL 50% 0 t OUTA t LH 1.5 OUTB 1.5 Figure 2 ARINC 429 Input to Logic Output Switching Waveform Figure 3 DO160 Lightning Induced Transient oltage Waveform #3. oc = 600, Isc = 24 A, Frequency =1 MHZ +-20% TESTA OR B 1.5 Peak T1 = 6.4 us +-20% T2 = 70 us +-20% t TOH ttol 50% OUTA OR B T1 T2 t Figure 5 TEST Input to Logic Output Switching Waveform Figure 4 DO160 Lightning Induced Transient oltage Waveform #4. oc = 300, Isc = 60A LIGHTNING TRANSIENT NOTES: 1. oc = Peak Open Circuit oltage available at the calibration point. 2. Isc = Peak Short Circuit Current available at the calibration point. 3. Amplitude tolerances: +10%, -0%. 4. The ratio of oc to Isc is the generator source impedance to be used for generating the waveforms. /I Peak 50% 0 T1 T2 5A: T1 = 40 us +-20% T2 = 120 us +-20% 5B: T1 = 50 us +-20% T2 = 500 us +-20% t Figure 6 DO160 Lightning Induced Transient oltage Waveform # Device Engineering Inc. Page 6 of 8 DS-MW Rev B

7 ORDERING INFORMATION DEI PN MARKING (1) TEST INPUTS DEI1046A-TES-G DEI1046A-TMS-G Notes: DEI1046A-TES (e4) DEI1046A-TMS (e4) Table 6: Ordering Information TEMPERATURE RANGE PACKAGE SCREENING YES -55/+85 C 38L TSSOP G Standard YES -55/+125 C 38L TSSOP G Standard 1. All packages marked with Lot Code and Date Code. (e4) after Date Code denotes Pb Free category. Table 7: Screening Process SCREENING STANDARD ELECTRICAL TEST: ROOM TEMPERATURE 100% HIGH TEMPERATURE 85 C or 125 C LOW TEMPERATURE 0.65% AQL@-55 C PACKAGE DESCRIPTION Table 8: Package Characteristics REFERENCE CHARACTERISTIC ALUE 38L TSSOP G Q JA (4 layer PCB with Power Planes) 75 C/W Q JC JEDEC MOISTURE SENSITIITY LEEL LEAD FINISH MATERIAL / JEDEC Pb-free CODE Pb-Free DESIGNATION JEDEC REFERENCE (MSL) 15 C/W MSL 2 / 260 C NiPdAu e4 RoHS Compliant MO-153-BD Device Engineering Inc. Page 7 of 8 DS-MW Rev B

8 Figure 6 38L TSSOP Mechanical Outline DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose Device Engineering Inc. Page 8 of 8 DS-MW Rev B